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d a t a sh eet product speci?cation file under integrated circuits, ic20 1997 dec 12 integrated circuits p83cx80; P87C380 microcontrollers for monitors with ddc interface, auto-sync detection and sync proc.
1997 dec 12 2 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 contents 1 features 1.1 differences from the 80c51 core 1.2 memory 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 functional description 6.1 general 7 memory organization 7.1 program memory 7.2 internal data memory 7.3 additional special function registers 8 interrupts 8.1 priority level structure 8.2 how interrupts are handled 8.3 interrupt enable register (ie) 8.4 interrupt priority register (ip) 9 watchdog timer 10 input/output (i/o) 10.1 the alternative functions for port 0, port 1, port 2 and port 3 10.2 emi (electromagnetic interference) reduction 11 reduced power modes 11.1 power control register 11.2 idle mode 11.3 power-down mode 11.4 status of external pins 12 oscillator 13 reset 13.1 external reset 13.2 power-on-reset 13.3 t2 (watchdog timer) overflow 14 analog control (dc) 14.1 8-bit pwm outputs (pwm0 to pwm9) 14.2 14-bit pwm output (pwm10) 14.3 a typical pwm output application 15 analog-to-digital converter (adc) 15.1 conversion algorithm 16 digital-to-analog converter (dac) 16.1 8-bit data registers for the dac outputs (dacn; n = 0 to 3) 17 display data channel (ddc) interface 17.1 special function registers related to the ddc interface 17.2 host type detection 17.3 ddc1 protocol 17.4 ddc2b protocol 17.5 ddc2ab/ddc2b+ protocol 17.6 ram buffer for the system and ddc application 18 i 2 c-bus interface 19 hardware mode detection 19.1 special function register for mode detection and sync separation 19.2 system description 19.3 system operation 20 power management 21 control modes 22 one time programmable (otp) version 23 limiting values 24 handling 25 dc characteristics 26 digital-to-analog converter characteristics 27 ac characteristics 28 package outline 29 soldering 29.1 introduction 29.2 soldering by dipping or by wave 29.3 repairing soldered joints 30 definitions 31 life support applications 32 purchase of philips i 2 c components
1997 dec 12 3 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 1 features 80c51 type core on-chip oscillator with a maximum frequency of 16 mhz (maximum 0.75 m s instruction cycle) a ddc interface: C that fully supports ddc1 with specific hardware C that is ddc2b, ddc2b+, ddc2ab (access.bus) compliant, based on a dedicated hardware i 2 c-bus interface. C contains a specific aux-ram buffer with programmable size (128 or 256 bytes) that can be used for ddc operation and shared as system ram automatic mode detection by hardware to capture the following information: C hsync frequency with 12-bit resolution C vsync frequency with 12-bit resolution C hsync and vsync polarity C hsync and vsync presence; needed for the vesa device power management signalling (dpms) standard on-chip sync processor comprising: C composite sync separation C free running mode C clamping C pattern generation two specific ports for the software i 2 c-bus interface 4 analog voltage outputs derived from an 8-bit digital-to-analog converter (dac) ten 8-bit pulse width modulation (pwm) outputs for digital control application one 14-bit pwm output for digital control application one 4-bit analog-to-digital converter (adc) with 2 input channels (for keyboard interface) led driver port (port 0); eight port lines with 10 ma drive capability one 8-bit port only for i/o function 20 derivative i/o ports with the specific port type configuration in each alternative function watchdog timer with a programmable interval on-chip power-on-reset for low power detection special idle and power-down modes for reduced power operation optimized for electromagnetic compatibility (emc) operating temperature: - 25 to +85 c single power supply: 4.4 to 5.5 v. 1.1 differences from the 80c51 core no external memory connection; signals ea, ale and psen are not present. port 1, port 2 and port 3 (p3.0 to p3.3 only) mixed with other derivative functions. timer 0/counter 0 and timer 1/counter 1: external input is removed. external interrupt 0/int0 replaced by mode detection function. standard serial interface (uart) and its control register are removed. wake-up from power-down mode is also possible by means of an interrupt. 1.2 memory table 1 rom/ram sizes device memory rom ram p83c880 8 kbytes 512 bytes p83c180 16 kbytes 512 bytes p83c280 24 kbytes 512 bytes p83c380 32 kbytes 512 bytes P87C380 (otp) 16 kbytes 512 bytes
1997 dec 12 4 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 2 general description the p83cx80; P87C380 denotes the following types: p83c880, p83c180, p83c280, p83c380 and P87C380, hereafter referred to as the p83c880, are monitor microcontrollers of the 80c51 family, with ddc (ddc1, ddc2b, ddc2b+ and ddc2ab) interface to the pc host. the internal hardware can separate composite sync signals and detect the various display modes. the digital/analog voltage outputs can be used to control the video and deflection functions the monitor. this data sheet details the specific properties of the p83c880, p83c180, p83c280, p83c380 and P87C380. the shared characteristics of the 80c51 family of microcontrollers are described in data handbook ic20 , which should be read in conjunction with this data sheet. 3 ordering information note 1. for emulation the package clcc84 is used. type number package (1) temperature range ( c) name description version p83c880 sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 - 25 to +85 p83c180 p83c280 p83c380 P87C380 (otp)
1997 dec 12 5 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 4 block diagram k, full pagewidth mgg021 4 10 4 xtal2 xtal1 p3 p2 p1 p0 parallel i/o ports & external bus 14-bit pwm watchdog timer (t2) two 16-bit timers (t0, t1) 80c51 core excluding rom/ram cpu program memory 10 8-bit pwm ddc interface mode detection int0 data memory 4 8-bit dac 4-bit adc software i 2 c-bus serial i/o 8-bit internal bus internal reset (4) 512 bytes ram p83c880 p83c180 p83c280 p83c380 P87C380 vsync in clamp (3) hsync in patout (3) scl1 (1) pwm0 to pwm7 (2) ; pwm8 to pwm9 (3) pwm10 (1) reset sda1 (1) hsync out (1) csync in (1) vsync out (1) v dd v ss v ssa v dda int1 int1 adc0 (3) dac0 to dac3 adc1 (3) sda (1) scl (1) fig.1 block diagram. (1) alternative function of port 1. (2) alternative function of port 2. (3) alternative function of port 3. (4) rom : 8 kbytes (p83c880); 16 kbytes (p83c180); 24 kbytes (p83c280); 32 kbytes (p83c380). eprom : 16 kbytes only in the p87c180a.
1997 dec 12 6 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 5 pinning information 5.1 pinning fig.2 pinning configuration for sdip42. handbook, halfpage mgg020 1 2 42 41 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pwm8/clamp/p3.0 pwm9/patout/p3.1 pwm10/p1.7 scl/p1.0 sda/p1.1 scl1/p1.2 sda1/p1.3 int1/v pp adc1/p3.3 adc0/p3.2 v dda v ssa dac3 dac2 dac1 dac0 reset p0.0 p0.1 p0.2 p0.3 pwm7/p2.7 pwm6/p2.6 pwm5/p2.5 pwm4/p2.4 pwm3/p2.3 pwm2/p2.2 pwm1/p2.1 pwm0/p2.0 xtal1 xtal2 v dd v ss hsync in /prog hsync out /p1.5 csync in /p1.6 vsync in /oe vsync out /p1.4 p0.7 p0.6 p0.5 p0.4 p83c880 p83c180 p83c280 p83c380 P87C380
1997 dec 12 7 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 5.2 pin description table 2 pin description for sdip42 (sot270-1) symbol pin description pwm9/patout/p3.1 41 pwm9 to pwm0 : 8-bit pulse width modulation outputs 9 to 0. pin 41 and 42 can also be used as the output pin of the test pattern display patout and clamping out signal clamp respectively; patout and clamp always have the higher priority. alternative function general i/o ports; port 3: p3.1 to p3.0 and port 2: p2.7 to p2.0 . pwm8/clamp/p3.0 42 pwm7/p2.7 1 pwm6/p2.6 2 pwm5/p2.5 3 pwm4/p2.4 4 pwm3/p2.3 5 pwm2/p2.2 6 pwm1/p2.1 7 pwm0/p2.0 8 xtal1 9 oscillator input pin for system clock. xtal2 10 oscillator output pin for system clock. v dd 11 digital power supply (+5 v). v ss 12 digital ground. hsync in / prog 13 horizontal sync input pin. during otp programming it is used as the program pulse input ( prog). hsync out /p1.5 14 horizontal sync output pin; alternative function: general i/o port p1.5. csync in /p1.6 15 composite sync input pin; alternative function: general i/o port p1.6. vsync in / oe 16 vertical sync input pin. during otp programming it is used as output strobe ( oe). vsync out /p1.4 17 vertical sync output pin; alternative function: general i/o port p1.4. p0.7 to p0.0 18 to 25 port 0: general i/o ports; capability to drive led. reset 26 reset input; active high initializes the device. dac0 to dac3 27 to 30 8-bit dac analog voltage output pins; output range: 0 to 5 v. v ssa 31 analog ground for dac and adc. v dda 32 analog power supply (+5 v) for dac and adc. adc0/p3.2 33 adc analog input pins; alternative function: general i/o ports p3.2 and p3.3. adc1/p3.3 34 int1/v pp 35 external interrupt input pin. during otp programming it is used as programming supply voltage pin; v pp = 12.75 v. sda1/p1.3 36 i 2 c-bus serial data i/o port for the ddc2 interface; alternative function: general i/o port p1.3. scl1/p1.2 37 i 2 c-bus serial clock i/o port for the ddc2 interface; alternative function: general i/o port p1.2. sda/p1.1 38 i 2 c-bus serial data i/o port; alternative function: general i/o port p1.1. scl/p1.0 39 i 2 c-bus serial clock i/o port; alternative function: general i/o port p1.0. pwm10/p1.7 40 14-bit pulse width modulation output 10; alternative function: general i/o port p1.7.
1997 dec 12 8 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 6 functional description this chapter gives a brief overview of the device. detailed functional descriptions are given in the following chapters: chapter 7 memory organization chapter 8 interrupts chapter 9 watchdog timer chapter 10 input/output (i/o) chapter 11 reduced power modes chapter 12 oscillator chapter 13 reset chapter 14 analog control (dc) chapter 15 analog-to-digital converter (adc) chapter 16 digital-to-analog converter (dac) chapter 17 display data channel (ddc) interface chapter 18 i2c-bus interface chapter 19 hardware mode detection chapter 20 power management chapter 21 control modes. 6.1 general the p83c880, p83c180, p83c280, p83c380 and P87C380 8-bit microcontrollers are manufactured in an advanced cmos process and are derivatives of the 80c51 microcontroller family. they have the same instruction set as the 80c51. they contain 512 bytes of data memory (ram). rom: 8 kbytes (p83c880); 16 kbytes (p83c180); 24 kbytes (p83c280); 32 kbytes (p83c380) and 16 kbytes of eprom for the p87c180. the microcontrollers are intended for use in monitors ranging from 14" to 21" that can be controlled from the outside (e.g. by a pc) via the external ddc interface. in addition to the 80c51 standard functions, they provide a number of dedicated hardware functions for monitor application. eight general i/o ports plus 20 functions combined i/o ports cater for application requirements adequately. ten sets of 8-bit pwm deliver the digital waveform for analog control purposes. one 14-bit pwm can support f to v application. the keyboard interface is achieved via a 4-bit adc. a watchdog timer with a maximum count period of 5 s prevents the processor running out of control due to malfunction. four channels of linear dac with 8-bit resolution support more accurate analog controls. one software i 2 c-bus interface is dedicated for the internal connection. a ddc interface will cover all ddc protocols, including ddc1, ddc2b, ddc2ab and ddc2b+. a hardware mode detector will facilitate mode detection even in power reduced modes, e.g. idle mode. the versatile hsync and vsync outputs can be generated to serve the desired application. in the free running mode, two display patterns can highlight the status of the monitor. accordingly, the following items will be supported by these microcontrollers: mode detection for: C horizontal sync (hsync) frequencies from below 15 khz up to 150 khz C vertical sync (vsync) frequencies from below 40 hz up to 200 hz access.bus interfacing with external devices, e.g. pcs ddc1, ddc2b, ddc2ab and ddc2b+ protocols as defined in the vesa ddc standard device power management signalling (dpms) as described in vesa dpms proposal. figure 1 shows the block diagram functions.
1997 dec 12 9 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 7 memory organization the central processing unit (cpu) manipulates operands in two memory spaces. there are 512 bytes of internal data memory, consisting of 256 bytes standard ram and 256 bytes ram buffer which is accessible as the auxiliary ram (aux-ram) or addressed through ddcadr and rambuf. the memory map and address spaces are shown in fig.3. 7.1 program memory the program memory consists of rom: 8 kbytes (p83c880), 16 kbytes (p83c180), 24 kbytes (p83c280) and 32 kbytes (p83c380). the program memory implemented in the P87C380 is a 16 kbytes eprom (otp). 7.2 internal data memory the internal data memory is divided into three physically separated parts: 256 bytes of ram, 256 bytes of aux-ram, and a 128 bytes special function registers (sfrs) area. these can be addressed each in a different way as described in sections 7.2.1 to 7.2.3 and table 3. table 3 internal data memory map notes 1. ram locations 0 to 127 can be addressed directly and indirectly as in the 80c51. 2. ram locations 128 to 255 can only be addressed indirectly. memory location address mode pointers direct indirect ram 0 to 127 (1) x x address pointers are r0 and r1 of the selected register bank 128 to 255 (2) - x aux-ram 0 to 255 - x (3) address pointer ddcadr and rambuf sfrs 128 to 255 x -- a ndbook, full pagewidth mgg028 overlapped space 255 127 0 internal program memory area internal data memory area 32767 (1) 24575 (2) 16383 (3) 8191 (4) 0 indirect only indirect only direct and indirect special function registers aux-ram buffer 255 0 fig.3 memory map and address spaces. (1) p83c380 and P87C380. (2) p83c280. (3) p380c180. (4) p83c880.
1997 dec 12 10 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 3. indirect-addressable via movx-datapointer or movx-ri instructions. 7.2.1 ram four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. the stack can be located anywhere in the internal 256 bytes ram. the stack depth is only limited by the available internal ram space of 256 bytes (see fig.4). 7.2.2 s pecial f unction r egisters (sfr s ) the sfrs can only be addressed directly in the address range from 128 to 255 (see fig.3). figure 5 gives an overview of the special function registers space. sixteen address in the sfrs space are both byte and bit-addressable. the bit-addressable sfrs are those whose address ends in 0h and fh. the bit addresses in this area are 80h to ffh 7.2.3 aux-ram aux-ram buffer 0 to 255 is indirectly addressable as external data memory locations 0 to 255 via movx-datapointer instruction or via movx-ri instruction. since the external access function is not available, any access to aux-ram 0 to 255 will not affect the ports. the 256 bytes of aux-ram buffer used to support ddc interface is also available for system usage by indirect addressing through the address pointer ddcadr and data i/o buffer rambuf. the address pointer (ddcadr) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to chapter 17). however, it is also possible to address the aux-ram buffer through movx command as usually used in the internal ram extension of 80c51 derivatives. fig.4 ram bit addresses. mbh079 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 18h 17h 10h 0fh 08h 07h 00h 24 23 31 16 15 8 7 0 bank 0 bank 1 bank 2 bank 3 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 (msb) (lsb) 255 ffh 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh byte address (decimal) byte address (hex) bit address (hex)
1997 dec 12 11 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 handbook, full pagewidth mgg029 ff (msb) (lsb) 255 mdcst ffh f8h byte address (decimal) byte address (hex) bit address (hex) fe fd fc fb fa f9 f8 f7 b f0h f6 f5 f4 f3 f2 f1 f0 ef pwme2 e8h ee ed ec eb ea e9 e8 c7 dfcon c0h c6 c5 c4 c3 c2 c1 c0 bf ip0 b8h be bd bc bb ba b9 b8 b7 p3 b0h b6 b5 b4 b3 b2 b1 b0 af ien0 a8h ae ad ac ab aa a9 a8 a7 p2 a0h a6 a5 a4 a3 a2 a1 a0 9f not used 98h 9e 9d 9c 9b 9a 99 98 97 p1 90h 96 95 94 93 92 91 90 8f tcon 88h 8e 8d 8c 8b 8a 89 88 87 p0 80h 86 85 84 83 82 81 80 e7 acc e0h e6 e5 e4 e3 e2 e1 e0 df s1con d8h psw d0h pwme1 c8h de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cf ce cd cc cb ca c9 c8 fig.5 special function registers bit addresses.
1997 dec 12 12 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 7.3 additional special function registers the standard sfrs as used in 80c51 and the sfrs for some typical derivative functions like i 2 c-bus interface, timer, etc. are described in the data handbook ic20 . the specific sfrs for the p83c880 are introduced in the relevant chapters. some sfrs which are not mentioned or not dedicated to a certain function will be described in the following sections. all new additional sfrs used in the p83c880 are listed in table 4. however, only some of them will be explained in detail in sections 7.3.1 to 7.3.7. table 4 overview of additional sfrs notes 1. x = dont care; even if its implemented. 2. b = both read/write and r o = read only; accessible for the entire byte or an individual bit. u = not implemented. register description address reset value (1) read/write (2) rambuf ram buffer i/o interface register 9ch xxxxxxxx b ddccon ddc control register 9dh x 00 x 0000 ubbubbbb ddcadr ddc address pointer 9eh 00000000 b ddcdat data shift register for ddc1 9fh 00000000 b dfcon miscellaneous control register c0h 10000000 b adcdat adc control register c1h xx 000000 uubbbbbr o pwm10h pwm high-byte data latch c6h 00000000 b pwm10l pwm low-byte data latch c7h 10000000 b s1con control register for ddc2 d8h 00000000 b s1sta status register for ddc2 d9h 11111000 r o s1dat data shift register for ddc2 dah 00000000 b s1adr address register for ddc2 dbh 00000000 b pwme1 pwm output control register 1 c8h 00000000 b pwme2 pwm output control register 2 e8h 00000000 b pwm0 to pwm9 data latches for 8-bit pwms c9h to cfh, edh to efh 00000000 b dac0 to dac3 8-bit data latches for 8-bit dacs e9h to ech 00000000 b hfp free run control register for hsync out f6h 01100000 b hfpopw free run and pulse width for hsync out f7h 00011111 b mdcst mode detect control and status register f8h 1 x 000000 bubbrrrr vfp free run control register for vsync out f9h 01000000 b vfpopw free run and pulse width for vsync out fah xx 000101 b pulcnt pulse generation control register fbh 00000000 b hfhigh horizontal period counting high-byte register fch 00000000 r o vfhigh vertical period counting high-byte register fdh 00000000 r o vflhfl vertical and horizontal period counting low-nibbles register feh 00000000 r o t2 watchdog timer data register ffh 00000000 b
1997 dec 12 13 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 7.3.1 ram b uffer i/o i nterface r egister (rambuf) rambuf is used as an i/o interface to the ram buffer. if it is associated with the address pointer ddcadr which is equipped with the capability of post increment, then it will be convenient to transfer the consecutive data stream. this feature is useful to support the ddc/edid data transfer. table 5 ram buffer i/o interface register (sfr address 9ch) table 6 description of rambuf bits 7.3.2 m iscellaneous c ontrol r egister (dfcon) this register is bit-addressable. table 7 miscellaneous control register (sfr address c0h) table 8 description of dfcon bits 76543210 rambuf.7 rambuf.6 rambuf.5 rambuf.4 rambuf.3 rambuf.2 rambuf.1 rambuf.0 bit symbol description 7 to 0 rambuf.7 to rambuf.0 8-bit data which is read from or to be written into ram buffer 76543210 ew2 soge synce ddce s1e adce p14lvl p8lvl bit symbol description 7 ew2 watchdog timer enable ?ag . this ?ag is associated with the ?ags, ew1 (sfr pwm10h) and ew0 in (sfr pwm10l) to form the enable/disable control key for the watchdog timer (see chapter 9). the watchdog timer is only disabled by ew2 to ew0 = 101, else it is kept enabled for the rest of the combinations. 6 soge csync in enable for pin csync in /p1.6 . if soge = 1, the pin function is csync in . if soge = 0, the pin function is i/o port p1.6. 5 synce sync separated signals output enable for pins vsync out /p1.4 and hsync out /p1.5. if synce = 1, the pins function as vsync out and hsync out respectively. if synce = 0, the pins function as i/o ports p1.4 and p1.5 respectively. 4 ddce enable for ddc interface pins scl1/p1.2 and sda1/p1.3 . if ddce = 1, the pins function as scl1 and sda1 respectively for the ddc interface. if ddce = 0, the pins function as i/o ports p1.2 and p1.3 respectively. 3 s1e enable for i 2 c-bus interface pins scl/p1.0 and sda/p1.1 . if s1e = 1, the pins function as scl and sda respectively for the i 2 c-bus interface. if s1e = 0, the pins function as i/o ports p1.0 and p1.1 respectively.
1997 dec 12 14 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 7.3.3 adc c ontrol r egister (adcdat) table 9 adc control register (sfr address c1h) table 10 description of adcdat bits 7.3.4 14- bit pwm data latches (pwm10h and pwm10l) table 11 pwm high-byte data latch (pwm10h; sfr address c6h) table 12 description of pwm10h bits 2 adce adc channel enable . this ?ag enables the adc function and also switches the pins adc0/p3.2 and adc1/p3.3 to the adc inputs function. if adce = 1, the adc function is enabled and the pin functions are adc0 and adc1 respectively. if adce = 0, the adc function is disabled and the pin functions are i/o ports p3.2 and p3.3 respectively. 1 p14lvl polarity selection bit for the pwm10 output (14-bit pwm) . if p14lvl = 1, pwm10 output is inverted. if p14lvl = 0, pwm10 output is not inverted. 0 p8lvl polarity selection bit for the pwm0 to pmm9 outputs (8-bit pwm) . if p8lvl = 1, pwm0 to pwm9 outputs are inverted. if p8lvl = 0, pwm0 to pwm9 outputs are not inverted. 76543210 -- dachl dac3 dac2 dac1 dac0 comp bit symbol description 7 to 6 - reserved. 5 dachl adc input channels selection . if dachl = 1, then input channel adc1 is selected. if dachl = 0, then input channel adc0 is selected. 4 to 1 dac3 to dac0 reference voltage level selection . the 4 bits select the analog output voltage (v ref ) of the 8-bit dac. for v ref values see table 31. 0 comp comparison result; read only . if comp = 1, then the adc input voltage is higher than the reference voltage. if comp = 0, then the adc input voltage is lower than the reference voltage. 76543210 ew1 pwm10h.6 pwm10h.5 pwm10h.4 pwm10h.3 pwm10h.2 pwm10h.1 pwm10h.0 bit symbol description 7 ew1 watchdog timer enable ?ag . this ?ag is associated with the ?ag ew2 (sfr dfcon) and ew0 (sfr pwm10l) to form the enable/disable control key for the watchdog timer; see tables 8 and 14. 6 to 0 pwm10h.6 to pwm10h.0 7 upper data bits for the 14-bit pwm. bit symbol description
1997 dec 12 15 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 table 13 pwm low-byte data latch (pwm10l; sfr address c7h) table 14 description of pwm10l bits 7.3.5 pwm o utput c ontrol r egister 1 (pwme1) table 15 pwm output control register 1 (sfr address c8h) table 16 description of pwme1 bits 76543210 ew0 pwm10l.6 pwm10l.5 pwm10l.4 pwm10l.3 pwm10l.2 pwm10l.1 pwm10l.0 bit symbol description 7 ew0 watchdog timer enable ?ag . this ?ag is associated with the ?ag ew2 (sfr dfcon) and ew1 (sfr pwm10h) to form the enable/disable control key for the watchdog timer; see table 8 and 12. 6 to 0 pwm10l.6 to pwm10l.0 7 lower data bits for the 14-bit pwm. 76543210 pwme1.7 pwme1.6 pwme1.5 pwme1.4 pwme1.3 pwme1.2 pwme1.1 pwme1.0 bit symbol description 7 to 0 pwme1.7 to pwme1.0 pwm outputs enable; n=7to0 . if pwme1.n = 1, the corresponding pwm is enabled and pins pwmn/p2.n are switched to pwmn outputs. if pwme1.n = 0, the corresponding pwm is disabled and pins pwmn/p2.n are switched to i/o ports p2.n function.
1997 dec 12 16 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 7.3.6 pwm o utput c ontrol r egister 2 (pwme2) table 17 pwm output control register 2 (sfr address e8h) table 18 description of pwme2 bits 7.3.7 d ata l atches for 8- bit pwm s (pwm0 to pwm9) table 19 data latches for 8-bit pwms (n = 0 to 9; sfr address c9h to cfh and edh to efh) table 20 description of pwm0 to pwm9 bits 76543210 patena dace3 dace2 dace1 dace0 pwme2.2 pwme2.1 pwme2.0 bit symbol description 7 patena patout (pattern output) enable . if patena = 1, the pin pwm9/patout/p3.1 is switched to the patout (display test pattern) output. if patena = 0, the patout function is disabled. the patout function always overrides other alternative functions such as pwm9 and p3.1. 6 to 3 dace3 to dace0 dac outputs enable ( n=3to0) . if dacen = 1, the corresponding dacs: dac3 to dac0 are enabled. if dacen = 0, the corresponding dacs: dac3 to dac0 are disabled. 2 to 0 pwme2.2 to pwme2.0 pwm outputs enable; n = 2 to 0 . if pwme2.n = 1, the corresponding pwms: pwm8, pwm9 and pwm10, are enabled by pwme2.2, pwme2.1 and pwme2.0 respectively and pins pwm8/clamp/p3.0, pwm9/patout/p3.1 and pwm10/p1.7 are switched to pwm output. if pwme2.n = 0, the corresponding pwm is disabled. pins pwm8/clamp/p3.0, pwm9/patout/p3.1 and pwm10/p1.7 are switched to i/o port functions p3.0, p3.1 and p1.7 respectively. 76543210 pwmn.7 pwmn.6 pwmn.5 pwmn.4 pwmn.3 pwmn.2 pwmn.1 pwmn.0 bit symbol description 7 to 0 pwmn.7 to pwmn.0 8-bit data for pwm channel n (n = 0 to 9)
1997 dec 12 17 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 8 interrupts the p83c880 has 5 interrupt sources; these are shown in fig.6. interrupt int1 is generated as in a normal 80c51 device. by means of it1 in sfr tcon this interrupt can be selected to be: level sensitive, when it1 = low; int1 must be inactive before a return from interrupt instruction (reti) is given, otherwise the same interrupt will occur again. edge sensitive, when it1 = high; the internal hardware will reset the latch when the lcall instruction is executed for the vector address (see table 21). interrupt int0 is generated by the mode change of mode detector. interrupt int0 is selected as edge or level sensitive by the state of the it0 bit in the sfr tcon. however, it is recommended to always set it0 to high (edge sensitive) so that ie0 will be reset by the internal hardware when the lcall instruction is executed for the vector address. timer 0 and timer 1 interrupts are generated by tf0 and tf1 which are set by an overflow of their respective timer/counter registers (except for timer 0 in mode 3; see data handbook ic20; 80c51 family; chapter timer/counters ). when a timer interrupt is generated, the interrupt flag is cleared by the internal hardware when the lcall instruction is executed for the vector address. the ddc interrupt is generated either by bit si (sfr s1con) for ddc2b/ddc2ab/ddc2b+ protocols or by bit ddc_int (sfr ddccon) or by bit swhint (sfr ddccon). these flags must be cleared by software. all bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is, interrupts can be generated or pending interrupts can be cancelled in software. each of these interrupts sources can be individually enabled or disabled by setting or clearing the bit in special function register ie (see table 23). ie also contains a global disable bit ea, which disables all interrupts at once. 8.1 priority level structure the priority level of each interrupt source can be individually programmed by setting or clearing a bit in special function register ip (see table 25). a low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. a high priority interrupt can not be interrupted by another interrupt source. if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if request of the same priority level is received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined as shown in table 21. the ip register contains a number of reserved (in 80c51) bits: ip.7, ip.6 and ip.4. user software should not write logic 1s to these positions, since they may be used in other 80c51 family products. table 21 priority within levels note 1. the priority within level structure is only used to resolve simultaneous requests of the same priority level. source priority within level (1) ie0 1 (highest) si 2 tf0 3 ie1 4 tf1 5 (lowest)
1997 dec 12 18 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.6 interrupt sources. handbook, full pagewidth mgg024 tf0 tf0 '0' '1' interrupt sources timer 0 overflow timer 1 overflow tf1 chreq tf1 s12 ddc int swh int si ie1 ie1 it1 int1 mux '0' '1' ie0 ie0 it0 int0 mux external interrupt int1 ddc2 (ddc2b/ddc2ab/ddc2b + ) interrupt ddc1 interrupt switch interrupt mode change interrupt
1997 dec 12 19 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 8.2 how interrupts are handled the interrupt flags are sampled at the s5p2 state of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware generated lcall is not blocked by any of the following conditions: 1. an interrupt of equal priority or higher priority level is already in progress. 2. the current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. the instruction in progress is reti or any write to the ie or ip registers. any of these conditions will block the generation of the lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie or ip, then at least one more instruction will be executed before the interrupt is vectored to.the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cycle. note that if an interrupt flag is active but not being responded to for one of the above mentioned conditions, and if the flag is still inactive when the blocking condition is removed, then the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the polling cycle/lcall sequence is illustrated in data handbook ic20; 80c51 family hardware description; figure: interrupt response timing diagram . note that if an interrupt of higher priority level becomes active prior to s5p2 of the machine cycle labelled c3 (see data handbook ic20; 80c51 family hardware description; figure: interrupt response timing diagram ), then in accordance with the above rules it will be vectored to during c5 and c6, without any instruction of the lower priority routine having been executed. thus the processor acknowledges an interrupt request by executing a hardware generated lcall to the appropriate servicing routine. the hardware generated lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to as shown in table 22. execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note that a simple ret instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. table 22 vector addresses source vector address ie0 0003h si 002bh tf0 000bh ie1 0013h tf1 001bh
1997 dec 12 20 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 8.3 interrupt enable register (ie) table 23 interrupt enable register (sfr address a8h) table 24 description of ie bits 8.4 interrupt priority register (ip) table 25 interrupt priority register (address b8h) table 26 description of ip bits 76543210 ea - es1 - et1 ex1 et0 ex0 bit symbol function 7ea disable all interrupts . if ea = 0, then no interrupt will be acknowledged. if ea = 1, then each interrupt source is individually enabled or disabled by setting or clearing its enable bit. 6 - reserved. 5 es1 enable ddc interface interrupt . if es1 = 1, then ddc interface interrupt is enabled. if es1 = 0, then ddc interface interrupt is disabled. 4 - reserved. 3 et1 enable timer 1 over?ow interrupt . if et1 = 1, then the timer 1 interrupt is enabled. if et1 = 0, then the timer 1 interrupt is disabled. 2 ex1 enable external interrupt 1 . if ex1 = 1 then the external 1 interrupt is enabled. if ex1 = 0 then the external 1 interrupt is disabled. 1 et0 enable timer 0 over?ow interrupt . if et0 = 1 then the timer 0 interrupt is enabled. if et0 = 0 then the timer 0 interrupt is disabled. 0 ex0 enable mode change . if ex0 = 1 then the mode change interrupt is enabled. if ex0 = 0 then the mode change interrupt is disabled. 76543210 -- ps1 - pt1 px1 pt0 px0 bit symbol description 7to6 - reserved. 5 ps1 ddc interface interrupt priority level . when ps1 = 1, ddc interface interrupt is assigned a high priority level. 4 - reserved. 3 pt1 timer 1 over?ow interrupt priority level . when pt1 = 1, timer 1 over?ow interrupt is assigned a high priority level. 2 px1 external interrupt 1 priority level . when px1 = 1, external interrupt 1 priority is assigned a high priority level. 1 pt0 timer 0 over?ow interrupt priority level . when pt0 = 1, timer 0 over?ow interrupt is assigned a high priority level. 0 px0 mode change interrupt priority level . when px0 = 1, mode change interrupt is assigned a high priority level.
1997 dec 12 21 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 9 watchdog timer in addition to the standard timers, a watchdog timer consisting of an 10-bit prescaler and an 8-bit timer is also incorporated. the timer is increased every 19.5 ms for an oscillator frequency of 16 mhz; this is derived from the oscillator frequency (f clk ) by the formula: when a timer overflow occurs, the microcontroller is reset. to prevent a system reset, the timer must be reloaded before an overflows occurs, by the application software. if the processor suffers a hardware/software malfunction, the software will fail to reload the timer. this failure will produce a reset upon overflow thus preventing the processor running out of control. the watchdog timer can only be reloaded if the condition flag wle (pcon.4) has been previously set by software. at the moment the counter is loaded the condition flag is automatically cleared. in the idle mode the watchdog timer and reset circuitry remain active. the time interval between timer reloading and the occurrence of a reset, depends on the reloaded value. f timer f clk 304 1024 ----------------------------- = the watchdog timers time interval is: where t2 = decimal value of the t2 register contents and t 1 = 15.2 m s (f clk = 10 mhz); t 1 = 12.7 m s (f clk = 12 mhz) and t 1 =19 m s (f clk = 16 mhz). for example, this may range from 19.5 ms to 5.0 s when using an oscillator frequency of 16 mhz. table 27 lists the resolution and the maximum time interval of the watchdog timer using different system clocks. the watchdog timer is controlled by the watchdog control bits: ew2; dfcon.7 (sfr address c0h) ew1; pwm10h.7 (sfr address c6h) ew0; pwm10l.7 (sfr address c6h). only when ew2 to ew0 = 101 the watchdog timer is disabled and allows the power-down mode to be enabled. the rest of pattern combinations will keep the watchdog timer enabled and disable the power-down mode. this security key with multiple flags split in two sfrs will prevent the watchdog timer from being terminated abnormally when the function of the watchdog timer is needed. tt 1 1024 256 t2 C () ----------------------------- = table 27 resolution and the maximum time interval of the wdt f clk (mhz) prescaler factor resolution (ms) maximum time interval (s) 10 152 15.56 4.0 12 12.97 3.3 16 304 19.46 5.0
1997 dec 12 22 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 10 input/output (i/o) the p83c880 has three 8-bit ports. ports 0 to 2 are the same as in the 80c51, with the exception of the additional functions of port 1 and port 2. port 3 only contains 4 bits. port 3 also has alternative functions. all ports are bidirectional. pins of which the alternative function is not used may be used as normal bidirectional i/os. the use of port 1, port 2 and port 3 pins as an alternative function is carried out automatically by the p83c880 provided the associated special function register bit is set high. the quasi-bidirectional type of port is applied for port 1, port 2 and port 3. port 0 is an open-drain i/o port with the capability to drive led. however, for any port with an alternative function, while the alternative function is performed, the port type will be switched to the appropriate type against a specific function. the port types: quasi-bidirectional, pull-up and open-drain are shown in figs 7, 8 and 9 respectively. 10.1 the alternative functions for port 0, port 1, port 2 and port 3 port 0 provides the low-order address in programming/verify mode for the P87C380. port 1 used for a number of special functions: 2 i/o pins for i 2 c-bus interface: scl/p1.0 and sda/p1.1. the port type in this situation is set as open-drain. 2 i/o pins for ddc interface: scl1/p1.2 and sda1/p1.3. the port type in this situation is set as open-drain. 2 i/o pins for the outputs of sync separation: vsync out /p1.4 and hsync out /p1.5. the port type in this situation is set as push-pull. one pin for the composite sync input of sync on green mode: csync in /p1.6. there is no pull-up protection diode for this input pin. one pin for the 14-bit pwm output: pwm10/p1.7. as pwm function, the port type is open-drain. port 2 two alternative functions are provided: high-order address in programming/verify mode for P87C380. 8 channels of pwm outputs: pwm0/p2.0 to p2.7/pwm7. the port type in this situation is set as open-drain. port 3 two alternative functions are provided: two channels of pwm output: pwm8/clamp/p3.0 and pwm9/patout/p3.1. the port type in this situation is set as open-drain. patout and clamp functions always override pwm or port function even if they are enabled. for the patout (pattern output) and clamp (clamping output) application, the port type is defined as push-pull. two pins for the software adc input: adc0/p3.2 and adc1/p3.3. they are analog inputs. 10.2 emi (electromagnetic interference) reduction in order to reduce emi (electromagnetic interference) the following design measures have been taken: slope control is implemented on all the i/o lines with alternative functions of the pwm, i 2 c-bus and ddc interface. for port pins p1.4 and p1.5, since the alternative functions vsync out and hsync out are incorporated, the driving capability is made as small as possible to reduce radiation and the slope control function is disabled to have a sharp output. rise and fall time (10% to 90%) for slope control are: t rf(min) < rise/fall time < t rf(max) . refer to chapter 27 for the detailed figures. placing the v dd and v ss pins next to each other double bonding of the v dd and v ss pins, i.e. 2 bondpads for each pin limiting the drive capability of clock drivers and prechargers applying slew rate controlled output drivers internal decoupling of the supply of the cpu core.
1997 dec 12 23 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.7 standard output with quasi-bidirectional port. handbook, full pagewidth mgg025 p1 p2 p3 input data read port pin 2 oscillator periods n strong pull-up i/o pin v dd i1 q from port latch input buffer fig.8 standard output with the pull-up current source. handbook, full pagewidth mgg026 p1 p2 p3 input data read port pin 2 oscillator periods n '1' strong pull-up i/o pin v dd i1 q from port latch input buffer fig.9 standard output with the open-drain port. handbook, full pagewidth mgg027 p1 p2 input data read port pin 2 oscillator periods n '0' strong pull-up i/o pin v dd i1 q from port latch input buffer
1997 dec 12 24 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 11 reduced power modes two software selectable modes of reduced power consumption are implemented. these are the idle mode and the power-down mode. 11.1 power control register (pcon) the idle mode and power-down mode are activated by software via the power control register (sfr pcon). its hardware address is 87h. pcon is not bit addressable. the reset value of pcon is 00h. 11.2 idle mode idle mode operation permits the interrupts, i 2 c-bus interface, ddc interface, mode detection and timer blocks t0, t1 and t2 (watchdog timer) to function while the cpu is halted. the following functions are switched off when the microcontroller enters the idle mode: cpu (halted) pwm0 to pwm10 (reset, output = high) 4-bit adc (aborted if conversion is in progress) dac0 to dac3 (output = indeterminate or frozen at the final value prior to the idle instruction; decided by software). the following functions remain active during idle mode; these functions may generate an interrupt or reset and thus terminate the idle mode: timer 0, timer 1 and timer 2 (watchdog timer) the ddc interface external interrupt mode detection. the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. the status of external pins during idle mode is shown in table 28. there are three ways to terminate the idle mode: activation of any enabled interrupt x0, t0, x1, t1 or s1 will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during idle mode. for example, the instruction that writes to pcon.0 can also set or clear both flag bits. when idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with an external hardware reset. since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 oscillator periods) to complete the reset operation. the third way of terminating the idle mode is by an internal watchdog reset. in all cases the microcontroller restarts after 3 machine cycles. 11.3 power-down mode in power-down mode the system clock is halted. the oscillator is frozen after setting the bit pd in the pcon register. the instruction that sets pcon.1 is the last executed prior to going into the power-down mode. once in power-down mode, the oscillator is stopped.the content of the on-chip ram and the special function registers are preserved. note that power-down mode can not be entered when the watchdog timer has been enabled. the power-down mode can be terminated by an external reset in the same way as in the 80c51 (but the sfrs are cleared due to reset) or in addition by the external interrupt, int1. a termination with int1 does not affect the internal data memory and the special function registers. this gives the possibility to exit from power-down without changing the port output levels. to terminate the power-down mode with an external interrupt, int1 must be switched to be level-sensitive and must be enabled. the external interrupt input signal int1 must be kept low till the oscillator has restarted and stabilized. the instruction following the one that put the device into the power-down mode will be the first one which will be executed after the wake-up.
1997 dec 12 25 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 11.4 status of external pins if the hsync out , vsync out , patout or clamp output is selected (for selection see description in tables 8 and 18) in idle or power-down mode, since sync separation is still alive in idle mode, hsync out , vsync out , patout or clamp output will be operating as normal. in power-down mode: hsync out , vsync out , patout or clamp output are pulled high. in idle or power-down mode, if bit ddce (sfr dfcon) is set, the function of p1.2 and p1.3 will be switched to the ddc interface pins scl1 and sda1 respectively. in idle mode scl1 and sda1 can be active only if ddc1 or ddc2 is enabled; otherwise these pins are in the high-impedance (high-z) state. if bit pwme.n (sfr pwme1/pwme2) is set, the function of p1.7, p2.n, p3.0 and p3.1 will be switched to the pwm output function. however, in both idle and power-down modes, the output of those pwm pins are pulled high. table 28 status of external pins during idle and power-down modes mode memory port0 to port 3 hsync; vsync; clamp; patout scl and sda scl1 and sda1 pwm0 to pwm10 dac0 to dac3 idle internal data operative high-z operative high unknown power-down internal data high high-z high-z high unknown
1997 dec 12 26 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 12 oscillator the oscillator circuit of the p83c880 is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output (see fig.10a). to drive the p83c880 externally, xtal1 is driven from an external source and xtal2 left open-circuit (see fig.10b). b. external clock drive. handbook, halfpage mbe312 xtal1 xtal2 n.c. external clock (not ttl compatible) fig.10 oscillator configurations. a. crystal oscillator; c = 20 pf. c. external clock drive for P87C380. handbook, halfpage xtal1 xtal2 external clock (not ttl compatible) mlc930 - 1 handbook, halfpage mbe311 xtal1 xtal2
1997 dec 12 27 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 13 reset there are three ways to invoke a reset and initialize the p83c880: via the external reset pin via the built-in power-on-reset circuitry via the watchdog timer overflow. figure 11 illustrates the reset mechanism. each reset source will activate an internal reset signal rstout. the cpu responds by executing an internal reset and puts the internal registers in a defined state as shown in table 29. table 29 reset values of the special function registers x = unde?ned. the internal ram is not affected by reset. address register content 80h p0 1111 1111 81h sp 0000 0111 82h dpl 0000 0000 83h dph 0000 0000 87h pcon 0000 0000 88h tcon 0000 0000 89h tmod 0000 0000 8ah tl0 0000 0000 8bh tl1 0000 0000 8ch th0 0000 0000 8dh th1 0000 0000 90h p1 1111 1111 9ch rambuf 0000 0000 9dh ddccon x00x 0000 9eh ddcadr 0000 0000 9fh ddcdat 0000 0000 a0h p2 1111 1111 a8h ien0 0x0x 0000 b0h p3 xxxx 1111 b8h ip0 xx0x 0000 c0h dfcon 1000 0000 c1h adcdat xx00 0000 c6h pwm10h 0000 0000 c7h pwm10l 1000 0000 c8h pwme1 0000 0000 c9h pwm0 0000 0000 cah pwm1 0000 0000 cbh pwm2 0000 0000 cch pwm3 0000 0000 cdh pwm4 0000 0000 ceh pwm5 0000 0000 cfh pwm6 0000 0000 d0h psw 0000 0000 d8h s1con 0000 0000 d9h s1sta 1111 000 dah s1dat 0000 0000 dbh s1adr 0000 0000 e0h acc 0000 0000 e8h pwme2 0000 0000 e9h dac0 0000 0000 eah dac1 0000 0000 ebh dac2 0000 0000 ech dac3 0000 0000 edh pwm7 0000 0000 eeh pwm8 0000 0000 efh pwm9 0000 0000 f0h b 0000 0000 f6h hfp 0110 0000 f7h hfpopw 0000 0101 f8h mdcst 1x00 0000 f9h vfp 0100 0000 fah vfpopw xx00 0101 fbh pulcnt 0000 0000 fch hfhigh 0000 0000 fdh vfhigh 0000 0000 feh vflhfl 0000 0000 ffh t2 0000 0000 address register content
1997 dec 12 28 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.11 on-chip reset configuration. handbook, full pagewidth mgg022 schmitt trigger reset circuitry r reset overflow timer t2 power-on-reset rstout 8 k w 10 m f v dd on-chip circuit reset poc 13.1 external reset pin reset is connected to a schmitt trigger for noise reduction (see fig.11). a reset is accomplished by holding the reset pin high for at least 16 machine cycles (192 system clocks) while the oscillator is running. an automatic reset can be obtained by switching on v dd , if the reset pin is connected to v dd via a capacitor and a resistor as illustrated in fig.11. the v dd rise time must not exceed 10 ms and the capacitor should be at least 10 m f. the decrease of the reset pin voltage depends on the capacitor and the external resistor r reset . the voltage must remain above the lower threshold for at least the oscillator start-up time plus 2 machine cycles. 13.2 power-on-reset an on-chip power-on-reset circuit that detects the supply voltage rise or fall and accordingly generates a power-on reset pulse (see fig.12). in the case of supply voltage rise, the power-on reset signal will follow the supply voltage rise; after reaching the trip level v t the power-on reset signal will maintain the same behaviour, and returns to a low state after a time interval t p . in the case of supply voltage fall, after the trip level v t is reached, the power-on reset signal will follow the waveform of the supply voltage for time interval t p . the time interval t p guarantees that a complete power-on reset pulse can trigger the internal reset signal. however, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the cpu for a further 2048 oscillator cycles. the values of v t , t p and a process tolerance of d v t can be found in chapter 25; currently v t = 3.9 v, t p =10 m s and d v t = 0.3 v. 13.3 t2 (watchdog timer data register) over?ow the length of the output pulse from t2 is 3 machine cycles. a pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible.
1997 dec 12 29 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.12 power-on reset switching level. handbook, full pagewidth mgg023 start-up 2048 clocks 2048 clocks t p t p supply voltage power-on-reset oscillator cpu running v t d v t
1997 dec 12 30 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 14 analog control (dc) the p83c880 has eleven pulse width modulated (pwm) outputs for analog control purposes e.g. brightness, contrast, e-w, r (or g or b) gain control etc. each pwm output generates a pulse pattern with a programmable duty cycle. the eleven pwm outputs comprise: 10 pwm outputs with 8-bit resolution (pwm0 to pwm9); described in section 14.1. 1 pwm output with 14-bit resolution (pwm10); described in section 14.2. a typical pwm output application is described in section 14.3. 14.1 8-bit pwm outputs (pwm0 to pwm9) pwm outputs pwm0 to pwm9 share the same pins as port lines p2.0 to p2.7, p3.0 and p3.1 respectively. selection of the pin function as either a pwm output or a port line is achieved using the appropriate pwmne bit in sfrs, pwme1 (address c8h) and pwme2 (address e8h); see table 4. the polarity of the pwm outputs is programmable and is selected by the p8lvl bit in sfr dfcon (address c0h); see table 4. the duty cycle of outputs pwm0 to pwm9 is dependent on the programmable contents of the data latches: sfrs pwm0 to pwm9. as the clock frequency of each pwm circuit is 1 4 f clk , the pulse width of the pulse generated can be calculated as: where (pwmn) is the decimal value held in the relevant data latch. the maximum repetition frequency of the 8-bit pwm outputs is: the block diagram for the 8-bit pwm outputs is shown in fig.13. pulse width 4 pwmn () f clk ---------------------------------- = f pwm f clk 1024 ------------ - = fig.13 block diagram for 8-bit pwms. handbook, full pagewidth mgg042 p2.x/p3.x data i/o p2.x/p3.x/pwmn 8-bit pwm data latch p8lvl internal data bus pwmne 8-bit dac pwm controller q q f clk 4
1997 dec 12 31 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.14 pwm0 to pwm9 output patterns. handbook, full pagewidth mgg043 256 1 2 3 m m + 1m + 2 256 1 00 01 m 255 decimal value pwm data latch 4 f clk 14.2 14-bit pwm output (pwm10) pwm10 shares the same pin as port line p1.7. selection of the pin function as either a pwm output or as a port line is achieved using the pwme2.0 bit in sfr pwme2 (address e8h); see table 4. the block diagram for the 14-bit pwm output is shown in fig.15 and comprises: two 7-bit latches; sfrs pwm10h and pwm10l 14-bit data latch (pwmreg) 14-bit counter coarse pulse controller fine pulse controller mixer. data is loaded into the 14-bit data latch (pwmreg) from the two 7-bit data latches (pwm10h and pwm10l) when pwm10h is written to. the upper seven bits of pwmreg are used by the coarse pulse controller and determine the coarse pulse width; the lower seven bits are used by the fine pulse controller and determine in which subperiods fine pulses will be added. the outputs out1 and out2 of the coarse and fine pulse controllers are then ored in the mixer to give the pwm10 output. the polarity of the pwm10 output is programmable and is selected by the p14lvl bit in sfr dfcon (address c0h); see section 7.3.2. as the 14-bit counter is clocked by 1 4 f clk , the repetition times of the coarse and fine pulse controllers may be calculated as shown below. coarse controller repetition time: fine controller repetition time: figure 16 shows typical pwm10 outputs, with coarse adjustment only, for different values held in pwm10h, when p14lvl = 1. figure 17 shows typical pwm10 outputs when p14lvl = 1, with coarse and fine adjustment, after the coarse and fine pulse controller outputs have been ored by the mixer. when p14lvl = 1, the pwm10 output is inverted. t sub 128 4 f clk ------ - = t r 128 128 4 f clk ------ - =
1997 dec 12 32 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.15 14-bit pwm block diagram. handbook, full pagewidth pwm10l pwm10h pwmreg ?ove instruction ?ov instruction data load timing pulse coarse 7-bit pwm fine pulse generator out2 out1 mixer q q p14lvl 14-bit counter q14 to 8 q7 to 1 polarity control bit pwm10 output f clk mgg044 7 7 7 7 load internal data bus 4
1997 dec 12 33 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 14.2.1 c oarse adjustment an active high pulse is generated in every subperiod; the pulse width being determined by the contents of pwm10h. the coarse output (out1) is high at the start of each subperiod and will remain high until the time [4/f clk (128 - pwm10h)] has elapsed. the output will then go low and remain low until the start of the next subperiod. the coarse pulse width may be calculated as: 14.2.2 f ine adjustment fine adjustment is achieved by generating an additional pulse in specific subperiods. the pulse is added at the start of the selected subperiod and has a pulse width of 4/f clk . the contents of pwm10l determine in which subperiods a fine pulse will be added. it is the logic 0 state of the value held in pwm10l that actually selects the subperiods. when more than one bit is a logic 1 then the subperiods selected will be a combination of those subperiods specified in table 30. pulse duration pwm10h () 4 f clk ------ - = for example, if pwm10l = 000 0101 then this is a combination of: pwm10l = 000 0001: subperiod 64 pwm10l = 000 0100: subperiods 16, 48, 80 and 112. pulses will be added in subperiods 16, 48, 64, 80 and 112. this example is illustrated in fig.18. when pwm10l holds 000 0000 fine adjustment is inhibited and the pwm10 output is determined only by the contents of pwm10h. table 30 additional pulse distribution pwm10l additional pulse in subperiod 000 000 1 64 000 0010 32 and 96 000 0100 16, 48, 80 and 112 000 1000 8, 24, 40, 56, 72, 88, 104 and 120 001 0000 4, 12, 20, 28, 36, 44, 52...116 and 124 010 0000 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 100 0000 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127 fig.16 pwm10 output patterns: coarse adjustment only. handbook, full pagewidth 127 0 1 2 128 - (m + 1) 128 - (m - 1) 128 - m 127 0 1 00 01 m 127 decimal value pwm7h data latch 4 f clk mgg045
1997 dec 12 34 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync p83cx80; P87C380 fig.17 pwm10 output patterns: coarse and fine adjustment (pwm10l = 000 0000b). handbook, full pagewidth mgg046 127 0 1 2 127 0 1 00 01 m 127 decimal value pwm10h data latch 4 f clk 128 - (m + 1) 128 - (m - 1) 128 - m fig.18 fine adjustment output (out2). handbook, full pagewidth mgg047 t sub0 t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127 t r 000 0001 000 0100 000 0101 pwm10l
1997 dec 12 35 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 14.3 a typical pwm output application a typical pwm application is shown in fig.19. the buffer is optionally used to reduce the influence from supply/ground bouncing to another circuit. r1 and c1 form the integration network, the time constant of which should be equal to or greater than 5 times the repetition period of the pwm output pattern. in order to smooth a changing pwm output a high value of c1 should be chosen. the value of c1 will normally be in the range 1 to 10 m f. the potential divider chain formed by r2 and r3 is used only when the output voltage is to be offset. the output voltages for this application are calculated using equations (1) and (2). (1) (2) the loop from the pwm pin through r1 and c1 to v ss will radiate high frequency energy pulses. in order to limit the effect of this unwanted radiation source, the loop should be kept short and a high value of r1 selected. the value of r1 will normally be in the range 3.3 to 100 k w . it is good practice to avoid sharing v ss (pin 12) with the return leads of other sensitive signals. v max r3 v dd r3 r1 r2 r1 r2 + ---------------------- + ------------------------------------ - = v min r1 r3 r1 r3 + --------------------- - v dd r2 r1 r3 r1 r3 + ---------------------- + --------------------------------------- = fig.19 typical pwm output circuit. a ndbook, halfpage mgg048 c1 r3 r1 r2 device type nr. (1) pwmn v ss supply voltage analog output (1) p83cx80; P87C380
1997 dec 12 36 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 15 analog-to-digital converter (adc) the adc inputs adc0 and adc1 share the same pins as port lines p3.2 and p3.3 respectively. selection of the pin function as either an adc input or as a port line is achieved using bit adce in sfr dfcon (address c0h). when adce = 1, the adc function is enabled; see section 7.3.2, table 8. the two channel adc comprises a 4-bit digital-to-analog converter (dac); a comparator; an analog channel selector and control circuitry. as the digital input to the 4-bit dac is loaded by software (a subroutine in the program), it is known as a software adc. the block diagram is shown in fig.20. the 4-bit dac analog output voltage (v ref ) is determined by the decimal value of the data held in bits dac0 to dac3 (dac value) of sfr adcdat (address c1h). v ref is calculated as: table 31 lists the v ref values as function of dac3 to dac0. when the analog input voltage is higher than v ref , the comp bit in sfr adcdat (address c1h) will be high. the channel selector, consisting of two analog switches, is controlled by bit dachl in sfr adcdat; see table 32. table 31 selection of v ref dac3 dac2 dac1 dac0 v ref (v) 0000 1 16 v dd 0001 2 16 v dd 0010 3 16 v dd 0011 4 16 v dd 0100 5 16 v dd 0101 6 16 v dd 0110 7 16 v dd 0111 8 16 v dd 1000 9 16 v dd 1001 10 16 v dd 1010 11 16 v dd 1011 12 16 v dd 1100 13 16 v dd 1101 14 16 v dd 1110 15 16 v dd 1111 v dd v ref v dd 16 ---------- dac value 1 + () = table 32 selection of adc channel 15.1 conversion algorithm there are many algorithms available to achieve the adc conversion. the algorithm described below and shown in fig.21 uses an iteration process. 1. select adcn channel for conversion. channel selection is achieved using bit dachl, sfr adcdat (address c1h). 2. set the digital input to the dac to 1000. the digital input to the dac is selected using bits dac3 to dac0 (sfr adcdat). 3. determine the result of the compare operation. this is achieved by reading the comp bit in sfr adcdat using the instruction mov a, adcdat. if comp = 1; the analog input voltage is higher than the reference voltage (v ref ). if comp = 0; the analog input voltage is lower than the reference voltage (v ref ). 4. if comp = 1; then the analog input voltage is higher than the reference voltage (v ref ) and therefore the digital input to the dac needs to be increased. set the input to the dac to 1100. 5. if comp = 0; then the analog input voltage is lower than the reference voltage (v ref ) and therefore the digital input to the dac needs to be decreased. set the input to the dac to 0100. 6. determine the result of the compare operation by reading the comp bit in sfr adcdat. 7. for the dac = 1100 case. if comp = 1; then the analog input voltage is still greater than v ref and therefore the digital input to the dac needs to be increased again. set the input to the dac to 1110. if comp = 0; then the analog input voltage is now less than v ref and therefore the digital input to the dac needs to be decreased. set the input to the dac to 1010. dachl channel selected 0 adc0 1 adc1
1997 dec 12 37 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 8. for the dac = 0100 case. if comp = 1; then the analog input voltage is now greater than v ref and therefore the digital input to the dac needs to be increased. set the input to the dac to 0110. if comp = 0; then the analog input voltage is still lower than v ref and therefore the digital input to the dac needs to be decreased again. set the input to the dac to 0010. 9. the operations detailed in 5, 6 and 7 above are repeated and each time the digital input to the dac is changed accordingly; as dictated by the state of the comp bit. the complete process is shown in fig.21. each time the dac input is changed the number of values which the analog input can take is reduced by half. in this manner the actual analog value is honed into. the value of the analog input (v a ) is determined by the formulae: as the conversion time of each compare operation is greater than 6 m s but less than 9 m s; a nop instruction is recommended to be used in between the instructions that select v ref ; the adc channel and read the comp bit. v a v dd 16 ---------- dac value 1 + () = fig.20 block diagram of the adc. handbook, full pagewidth 4-bit dac comparator dac3 dac2 dac1 dac0 adce dachl mgg049 adc enable selection dac value selection enable selector adc channel selector p3.2/adc0 p3.3/adc1 v ref en port interface en1 en0 mov a, adcdat instruction to read comp bit comp bit internal bus channel selection + -
1997 dec 12 38 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 handbook, full pagewidth mbk518 value = 0111 comp = 1 t + 0100 + 0010 - 0010 + 0001 + 0001 - 0001 - 0001 + 0010 - 0010 + 0001 + 0001 - 0001 - 0001 - 0100 f value = 1011 comp = 1 tf value = 1101 comp = 1 tf value = 1110 comp = 1 value = 1100 comp = 1 tf 1111 1110 tf 1101 1100 value = 1001 comp = 1 tf value = 1010 comp = 1 value = 1000 comp = 1 tf 1010 tf 1001 1000 1011 value = 0011 comp = 1 tf value =0101 comp = 1 tf value = 0110 comp = 1 value = 0100 comp = 1 tf 0111 0110 tf 0101 0100 value = 0001 comp = 1 tf value = 0010 comp = 1 value = 0000 comp = 1 tf 0010 tf 0001 0011 0000 fig.21 example of converting algorithm for software adc.
1997 dec 12 39 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 16 digital-to-analog converter (dac) four channels of linear voltage outputs mainly for the horizontal and vertical position control are provided from four sets of the digital-to-analog converter (dac). the dacs are well tuned to meet the following specific system requirements of the monitor. for a 21'' monitor, the shift per step by changing the data of the dac is expected to be 0.5 mm. accordingly, the dac with 8-bit resolution is required. to avoid visible position shift due to environmental temperature change, the drift of output level of the dac is less than 1.5 mv/ c. to eliminate the visible jitter, the maximum tolerable ripple for the output voltage of the dac is less than 2 mv. each dac comprises an 8-bit data latch, a voltage scaling mechanism and an output driver. a precise current reference is provided internally to serve 4 sets of dacs. the voltage sources with values weighted by 2 0 up to 2 7 are switched according to the data input so that the sum of the selected voltages gives the required analog voltage from the output driver. the range of the output voltage is approximately 0 to 5 v. however, to fulfil some special requirement for current driving capability, a very minor reduction (0.2 to 0.4 v) of the output voltage range is acceptable. the dac outputs are protected against short-circuits to v dda and v ssa . to avoid the possibility of oscillation, capacitive loading at the dac outputs should not exceed 10 pf. in reduced power modes like idle mode and power-down mode, the operation of the dacs can be disabled to save the power consumption. in that case, the outputs of the dacs are indeterminate. figure 20 illustrates the block diagram of the dac. 16.1 8-bit data registers for the dac outputs (dacn; n = 0 to 3) the dacs are individually programmed using an 8-bit word to select an output from one of 256 voltage steps. for v dda = 5 v, the maximum output voltage of all dacs is 5 v and the resolution is approximately 17.6 mv (5 v/256). at power-on all dac outputs are set to their lowest value: 00h (i.e. 0 v). the relevant sfrs for the dacs are described in table 33 and 34. table 33 8-bit data registers for the dac outputs (address e9h to ech) table 34 description of dacn bits 76543210 dacn.7 dacn.6 dacn.5 dacn.4 dacn.3 dacn.2 dacn.1 dacn.0 bit symbol description 7 to 0 dacn.7 to dacn.0 8-bit data for the dac; channel n ( n=0to3).
1997 dec 12 40 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.22 block diagram of the dac. handbook, full pagewidth mgg050 8 data latch (sfr address e9h) dac0 reference voltage/current generator dac1 data latch (sfr address eah) internal bus data latch (sfr address ebh) dac2 data latch (sfr address ech) dac3 dac0 dac1 dac2 dac3
1997 dec 12 41 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17 display data channel (ddc) interface the monitor typically includes a number of user controls to set picture size, position, colour balance, brightness and contrast. furthermore, to optimize some internal setting for different display modes, the timing characteristics should be acquired by the control side. for factory alignment, it is preferable to store the entire information in a non-volatile memory to facilitate production automation. normally, monitors provide hardware control panels or a keypad to perform this control. however, it is now popular for these controls to go to the pc host. therefore the communication between monitor and host becomes an issue. ddc1, ddc2b, ddc2b+ and ddc2ab (access.bus) emerge as a standard for monitor interface. p83c880 is compliant to ddc1, ddc2b, ddc2b+ and ddc2ab (access.bus). they also conform to the detection sequence defined by vesa and access.bus industry group and identify the protocol which they are communicating with. a transmitter clocked by the incoming vsync is dedicated for ddc1 operation. an i 2 c-bus interface hardware logic forms the kernel of ddc2b and ddc2ab. an address pointer, ddcadr (address 9eh), with post increment capability is employed to serve ddc1, ddc2b, ddc2b+ and ddc2ab modes. the conceptual block diagram is illustrated in fig.23. 17.1 special function registers related to the ddc interface table 35 sfrs related to the ddc interface 17.1.1 ddc m ode s tatus and ddc1 c ontrol r egister (ddccon) table 36 ddc mode status and ddc1 control register (address 9dh) address sfr remarks 9ch rambuf see section 7.3.1. 9dh ddccon ddccon, ddcadr and ddcdat are mainly created for the ddc1 protocol; they are explained in sections 17.1.1 to 17.1.3. 9eh ddcadr 9fh ddcdat d8h s1con one extra i 2 c-bus interface is used to serve ddc2b, ddc2b+ and ddc2ab. therefore s1con, s1sta, s1dat and s1adr are just the copies of the corresponding registers in the general i 2 c-bus interface. their usage is exactly the same. d9h s1sta dah s1dat dbh s1adr 76543210 - ex_dat swenb - ddc1_int ddc1enable swh_int m0
1997 dec 12 42 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 table 37 description of ddccon bits note 1. these bits are r/w. bit symbol description 7 - reserved. 6 ex_dat this bit de?nes the size of the edid data. it is related to the function of the post increment of the address pointer, ddcadr. when the upper limit is reached, the address pointer will wrap around to 00h. if ex_dat = 1, the data size is 256 bytes. if ex_dat = 0, the data size is 128 bytes; the addressing range for the edid data buffer is mapped from 0 to 127, the rest (128 to 255) can still be used by the system. 5 swenb this bit indicates if the software/cpu is needed to take care of the operation of ddc1 protocol. if swenb = 1, in ddc1 protocol, the cpu is interrupted during the period of the 9th transmitting bit so that the software service routine can update the hold register of the transmitter by moving new data from the appropriate area (it is not necessary to be the ram buffer). this transferring must be done within 40 m s. if swenb = 0, the hold register of the transmitter will be automatically updated from the ram buffer without the intervention of the cpu. 4 - reserved. 3 ddc1_int (1) interrupt request bit (002bh is assigned as the interrupt vector address). this bit is only valid in ddc1 protocol while software handling is enabled (swenb = 1). this bit is set by hardware and should be cleared by software in an interrupt service routine. if ddc1 is fully under the hardware control (swenb = 0), this bit can be ignored. if ddc1_int = 1, interrupt request is pending. if ddc1_int = 0, there are no interrupt request. 2 ddc1enable (1) ddc1 enable control bit. if ddc1enable = 1, ddc1 is enabled. if ddc1enable = 0, ddc1 is disabled (the activity on vclk is ignored). 1 swh_int (1) interrupt request bit (002bh is assigned as the interrupt vector address). this bit is used to indicate that ddc interface switches from ddc1 to ddc2 (i.e. the high-to-low transition is observed on pin scl1). this bit should be cleared by software in an interrupt service routine. if swh_int = 1, interrupt request is pending. if swh_int = 0, there is no interrupt request. 0m0 (1) ddc mode indication bit. if m0 = 0, ddc1 is set; if m0 = 1, ddc2 is set.
1997 dec 12 43 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17.1.2 a ddress p ointer for ddc i nterface r egister (ddcadr) the bits of this register are all r/w. table 38 address pointer for ddc interface register (address 9eh) table 39 description of ddcadr bits 17.1.3 ddc1 d ata t ransmission r egister (ddcdat) table 40 ddc1 data transmission register (address 9fh) table 41 description of ddcdat bits 76543210 ddcadr.7 ddcadr.6 ddcadr.5 ddcadr.4 ddcadr.3 ddcadr.2 ddcadr.1 ddcadr.0 bit symbol description 7 to 0 ddcadr.7 to ddcadr.0 address pointer with the capability of post increment. after each access to rambuf register (either by software or by hardware ddc1 interface), the content of this register will be increased by one. it is available both in ddc1, ddc2 (ddc2b, ddc2b+ and ddc2ab) and system operation. 76543210 ddcdat.7 ddcdat.6 ddcdat.5 ddcdat.4 ddcdat.3 ddcdat.2 ddcdat.1 ddcdat.0 bit symbol description 7 to 0 ddcdat.7 to ddcdat.0 data byte to be transmitted in ddc1 protocol.
1997 dec 12 44 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.23 ddc interface block diagram. handbook, full pagewidth mgg030 cr2 ens sta sto si aa cr1 cr0 0 0 0 sc0 sc1 sc2 sc3 sc4 bus clock generator shift register monitor address 0 1 7 ddc1 hold register ddc1 transmitter initialization synchronization arbitration logic s1adr(dbh) s1dat(dah) s1con(d8h) s1sta(d9h) ddc2b/ddc2ab/ddc2b + interface ddc1/ddc2 detection sio2 internal bus aux-ram buffer rambuf address pointer sda1 scl1 vclk (from s1con) si int (interrupt vector 002bh) ddcdat(9fh) ddc1 enable ddc1_int - - swh_int swenb ex_dat m0 ddccon(9dh) rambuf(9ch) ddcadr(9eh)
1997 dec 12 45 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17.2 host type detection the detection procedure conforms to the sequences proposed by vesa monitor display data channel (ddc) specification . the monitor needs to determine the type of host system: ddc1 or old type host ddc2b host (host is master, monitor is always slave) ddc2b+/ddc2ab (access.bus) host. the sequence of detection is described in the flow chart illustrated in fig.24. the monitor where p83c880 resides is always both ddc1 and ddc2 compatible with ddc2 having the higher priority. the display (i.e. p83c880) shall start transmitting ddc1 signals whenever it is switched on and vsync is applied to it from the host for the first time. the display shall switch to ddc2 within 3 system clocks as soon as it sees a high-to-low transition on the clock line (scl), indicating that there are both ddc2 devices connected to the bus. under that condition, the mode flag m0 will be changed from the default setting logic 0 to logic 1. accordingly, the interrupt will be invoked by setting flag swh_int (ddccon.1) as high (this flag must be cleared by the interrupt service routine). this procedure will cause a transmission error. however, both the display and the host shall have error detection and a method to recover from the temporary transmission errors. figure 24 illustrates the concept and interaction between the monitor and the host. after power-on, the ddc1enable bit (ddccon.2) is set by software, setting the monitor as a ddc1 device. therefore, the mode flag m0, is set as logic 0. following vsync as clock, the monitor (i.e. p83c880) will transmit edid data stream to the host. however, if ddc2 clock (scl clock) is present, the monitor will be switched to ddc2b device with the mode flags setting as logic 1. software will determine whether it is a ddc2b, ddc2b+, or ddc2ab protocol.
1997 dec 12 46 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 handbook, full pagewidth mgg031 is monitor ddc2b + /ddcab2 capable? respond to ddc2b + /ddcab2 command ddc2 communication is idle. monitor is waiting for a command no yes respond to ddc2b command yes is ddc2b + /ddcab2 command detected? no yes is command ddc2b command? no has a command been received? no yes monitor power-on stop sending of edid switch to ddc2 communication mode (1) no yes no is vsync present? is ddc2 clock present? edid sent continuously using vsync as clock communication is idle fig.24 host type detection. (1) once the monitor switches from ddc1 mode to ddc2 mode it will remain in ddc2 mode for the duration of that power-on period.
1997 dec 12 47 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17.3 ddc1 protocol the ddc1 is a primitive interface, but adopted by many monitor models and pc hosts. it is a point-to-point interface. the monitor is always set to transmit only mode. in the initialization phase, 9 clock cycles on the vclk pin will be given for the internal synchronization. during this period, the sda pin will be kept in the high-impedance state. by default, bit ddc1enable is reset as logic 0. it is advised to move the edid data to the ram buffer before enabling ddc1. to activate the ddc1 interface, ddc1enable flag is set to logic 1 and it is taken as granted that mode flag m0 is set at logic 0. if swenb is kept at the default value logic 0, the ram buffer will be tied to the ddc1 protocol. the allocated size from the ram buffer is decided by the flag ex_dat. if ex_dat is low, only 128 bytes are reserved to store ddc1 edid data. the upper part (locations 128 to 255) is still available to the system. if ex_dat is high, the entire 256 bytes of the ram buffer are dedicated to the usage of ddc1 operation. the hardware mechanism will automatically move new data from the defined ram buffer to the hold register of the transmitter with the aid of the address pointer ddcadr. within the range of ddc1 ram buffer, the function of the post increment is executed. if the upper limit is reached, the address pointer ddcadr will wrap around to 00h. however, if ex_dat = low, the lower part is occupied by the ddc1 operation and the upper part is still free to the system. nevertheless, the effect of the post increment just applies to the part related to the ddc1 operation. in other words, the system program is still able to address the locations from 128 to 255 in the ram buffer through the movx command but without the facility of the post increment; e.g. in case ex_dat = low and swenb = low, the system program might read one data byte from address 200 of the ram buffer by the following procedure: mov r0, #200; movx a, @r0. the address pointer ddcadr is tied to the ddc1 transmitter here. to avoid the interference to the content of ddcadr, it has to address the ram buffer through the movx command. while ex_dat = high, the entire ram buffer is covered by the pointing range of the address pointer ddcadr, with the capability of the post increment; no matter whether the access is done by ddc1 related hardware (swenb = 0) or software (swenb = 1). if swenb is set at logic 1, then after the valid synchronization, the ddc1 interrupt will be invoked (interrupt vector address 002bh). the service routine should fill the hold register ddcdat (sfr address 9fh) with the first data byte either from the internal rom (part of the system rom) or from the ram buffer. in the latter case, the address pointer ddcadr will provide the benefit of the post increment for the service routine to read/write the ddc1 edid data area. this action must be finished within 40 m s (40 machine cycles in 12 mhz system clock). ddc1_int flag must be cleared by software before it returns from service routine. on the rising edge of the 10th clock cycle, the device will output the first valid data bit which should be the most significant bit of a byte. the following data is also transmitted on the sda pin in 8 bits per byte format. each byte is followed by a 9th clock pulse during which time sda is left high-impedance and either the hardware mechanism (swenb = 0) or the service routine (swenb = 1) will update the hold register. the data bit is output on the rising edge of vclk, the most significant bit first. the address pointer is initialized at 00h. after writing a data byte to the hold register through hardware or software, it will be incremented by one automatically. if the address reaches 127 (ex_dat = 0) or 255 (ex_dat = 1) the address pointer will wrap around to the first location: 00h. nevertheless, it is possible for cpu (in software mode, i.e. swenb = 1) to write any desired address to the address pointer to proceed random access. the transaction in ddc1 protocol is shown in fig.25. if ddc1 hardware mode is used, the following ddc1 operation steps are recommended: 1. reset ddc1enable (by default ddc1enable is cleared to low after power-on reset). 2. set swenb to high. 3. depending on the data size of edid data, set ex_dat to low (128 bytes) or high (256 bytes). 4. use substantial moving commands (ddcadr, rambuf involved) to move the entire edid data to ram buffer. 5. reset swenb to low. 6. reset ddcadr to 00h. 7. set ddc1enable to high enabling the ddc1 hardware; during the synchronization phase (the first 9 vclk clocks) the first data byte will be loaded into the shift register of the transmitter through the hold register.
1997 dec 12 48 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.25 transmission protocol in ddc1 interface. handbook, full pagewidth mgg032 123456789123 1 4 56 7 89 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 high z 00 01 11 01 11 01 ddc1_int ddc1 enable scl sda vclk t su(ddc1) t vclkh t vclkl t dov high z 17.4 ddc2b protocol the ddc2b construction is based on the philips i 2 c-bus interface. however, in the level of ddc2b, pc host is fixed as the master and the monitor is always regarded as the slave. both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. for details of the i 2 c-bus interface, please refer to the philips publication the i 2 c-bus and how to use it ordering number 9398 393 40011 and/or the data handbook ic20 . in the p83c880, one more pair of i 2 c-bus pins scl1, sda1 and an i 2 c-bus hardware interface logic are dedicated to perform ddc2b/ddc2b+/ddc2ab protocols. the built-in address pointer mentioned in section 17.3 can be used to speed up the processing of service routines for the access of the internal rom or a dedicated ram buffer. according to the ddc2b specification: a0h (for write mode) and a1h (for read mode), are assigned as the default address of monitors. the reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the specified time limit. however, it is not necessary for edid data to be stored on-chip. it is also possible to have access to the external eeprom/rom through another set of i 2 c-bus interface and pre-store those data in the ram buffer. if software on the slave side cannot react to the master in time, based on i 2 c-bus protocol, scl pin can be stretched low to inhibit the further action from the master. the transaction can be proceeded in either byte or burst format.
1997 dec 12 49 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17.5 ddc2ab/ddc2b+ protocol ddc2ab/ddc2b+ is a superset of ddc2b. monitors that implement ddc2ab/ddc2b+ are full featured access.bus devices. essentially, they are similar to ddc2b. the i 2 c-bus interface forms the fundamental layer for both protocols. however, in ddc2ab/ddc2b+ the default address for monitors is assigned to 6eh instead of a0h and a1h in ddc2b. monitors and hosts can play both the roles of master and slave. under this kind of protocol, it is easy to extend the support for hosts to read vesa video display information format (vdif) and remotely control monitor functions. the read/write protocols can be the same as described in section 17.4. nevertheless, the command/information sequence between host and monitor must conform to the specification of access.bus. timing rules specified in access.bus such as maximum response time to reset message (<250 ms) from host, maximum time to hold scl low (<2 ms) etc., can be satisfied through software checks and built-in timers such as timer 0 and timer 1 in the p83c880. in ddc2ab/ddc2b+ the monitor itself can act as a master to activate the transaction. the default address assigned for the host is 50h. figure 26 shows the overview and relationship between software and the existing i 2 c-bus hardware for the ddc interface. fig.26 the conceptual structure of the ddc interface. handbook, full pagewidth mgg035 ddc interrupt vector address (002bh) mode = 1 check mode flag in ddccon mode = 0 ddc2b + /ddc2ab command received ddc2b command received ddc2b + /ddc2ab utilities ddc2b utilities i 2 c-bus service routines ddc1 utilities i 2 c-bus interface (hardware) ddc1 transmitter (hardware) swenb = 0 swenb = 1
1997 dec 12 50 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 17.6 ram buffer for the system and ddc application the architecture of the ram buffer is set up in a flexible configuration to use the ram resource to a maximum. in principle the ram buffer can be shared as system or ddc ram buffer. the relationship among those applications is arranged as shown in table 42. table 42 relation between system ram and ddc ram notes 1. read/write through movx instruction might conflict with the access from ddc1 hardware. so the access from cpu by using movx instruction is forbidden. 2. read/write through ddcadr and rambuf registers has the conflicting problem also. even the content of ddcadr, which should be employed by ddc1 hardware, will be damaged. so it is inhibited to use this type of access. 3. if ddcadr reaches 127 it will automatically wrap around to 0 after the access is done. 4. the access conflict can be avoided because ddc1 access is done by the interrupt service routine. however, the edid transferring from the ram buffer should be finished within 40 m s. 5. if ddcadr reaches 255 it will automatically wrap around to 0 after the access is done. 18 i 2 c-bus interface the p83c880 has a software i 2 c-bus interface that can be used in master mode. full details of the i 2 c-bus are given in the 80c51 family data handbook ic20 and/or the document the i 2 c-bus and how to use it (ordering number 9398 393 40011). the i 2 c-bus interface lines sda and scl share the same pins as port 1 lines p1.1 and p1.0 respectively; selection is done via the s1e bit in sfr dfcon (address c0h). mode ex_dat swenb aux ram 0 to 127 aux ram 128 to 255 normally reserved for note normally reserved for available for note ddc1 0 0 ddc1 edid data 1, 2 and 3 - system access 2 0 1 3 and 4 - 1 0 1 and 2 ddc1 edid data - 1, 2 and 5 1 1 4 4 and 5 ddc2 0 1 ddc2 edid data 3 - system access - 11 - ddc2 edid data - 5
1997 dec 12 51 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19 hardware mode detection due to the many restrictions for mode detection via software, a hardware mode detector is introduced in the p83c880. this feature has the following advantages: fast enough to react on any mode change. possibility to detect the polarity of hsync without extra input pin. higher accuracy to measure the hsync and vsync frequency relieves the cpu and valuable timers/counters in the microcontroller from lengthy mode detection in reduced power modes, e.g. idle mode, the mode detection is still active. apart from the above mentioned benefits, some extra features can be achieved through hardware mode detection. the composite sync separation can be done while mode detection continues. the various formats of hsync and vsync output pulses are provided to fit into different applications. since the information of the operational modes defined in device power management signalling (dpms) for monitors is embedded in hsync and vsync, the mode detector is also able to recognize the operational mode and generate the fixed free running frequency for hsync and vsync in some specific modes like stand-by, suspend and power-off. two display patterns, the white and the cross hatch, can be displayed for the self test in the free running mode. more on device power management signalling (dpms) will be explained in chapter 20, power management. 19.1 special function register for mode detection and sync separation there are 4 sfrs related to mode detection and sync separation: mdcst (sfr address f8h); hfhigh (sfr address fch); vfhigh (sfr address fdh) and vflhfl (sfr address feh). five sfrs are applied for the output pulse generation of hsync and vsync and the display pattern generation for the self test: hfp (sfr address f6h); hfpopw (sfr address f7h); vfp (sfr address f9h); vfpopw (sfr address fah) and pulcnt (sfr address fbh). these sfrs are described in detail in section 19.1.1 to 19.1.9. 19.1.1 m ode d etection / sync separation c ontrol and s tatus r egister (mdcst) table 43 mode detection/sync separation control and status register (sfr address f8h) table 44 description of mdcst bits 76543210 march chreq xsel hsel hpres vpres hpol vpol bit symbol description 7 march mode detection enable . if march = 1, mode detection is enabled. if march = 0, mode detection is disabled. default value march = 1 to guarantee that mode detection is automatically executed after power-on reset. 6 chreq polarity or frequency change. if chreq = 1 then the polarity or frequency change happened. the polarity or frequency is detected after a chreq high-to-low transition, because the mode change becomes stable after the chreq high-to-low transition. 5 xsel indicates if the clock used for the mode detection and the pulse generation is 1 2 f clk . if xsel = 1, the internal clock is 1 2 f clk . if xsel = 0 the internal clock is equal to f clk . 4 hsel indicates the horizontal sync input coming from hsync in (pin hsync in / prog) or csync in (pin csync in /p1.6). if hsel = 1, csync in is the input pin. if hsel = 0, hsync in is the input pin. 3 hpres indicates the presence of hsync. if hpres = 1, hsync is present. if hpres = 0, hsync is not present.
1997 dec 12 52 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.1.2 h orizontal p eriod c ounting h igh - byte r egister (hfhigh) table 45 horizontal period counting high-byte register (sfr address fch) table 46 description of hfhigh bits 19.1.3 v ertical p eriod c ounting h igh - byte r egister (vfhigh) table 47 vertical period counting high-byte register (sfr address fdh) table 48 description of vfhigh bits 19.1.4 v ertical and h orizontal p eriod c ounting l ow - nibbles r egister (vflhfl) table 49 register containing the low nibbles of the horizontal and vertical period counting (sfr address feh) table 50 description of vflhfl bits 2 vpres indicates the presence of vsync. if vpres = 1, vsync is present. if vpres = 0, vsync is not present. 1 hpol indicates the polarity of hsync. if hpol = 0, polarity is positive (active high; i.e. high at horizontal retracing period). if hpol = 1, polarity is negative (active low; i.e. low at horizontal retracing period). 0 vpol indicates the polarity of vsync. if vpol = 0, polarity is positive (active high; i.e. high at vertical retracing period). if hpol = 1, polarity is negative (active low; i.e. low at vertical retracing period). 76543210 hf.11 hf.10 hf.9 hf.8 hf.7 hf.6 hf.5 hf.4 bit symbol description 7 to 0 hf.11 to hf.4 indicate the high byte of the value counted by mode detector for 4 horizontal scanning periods. 76543210 vf.11 vf.10 vf.9 vf.8 vf.7 vf.6 vf.5 vf.4 bit symbol description 7 to 0 vf.11 to vf.4 indicate the high byte of the value counted by mode detector for 1 vertical ?eld/frame period. 76543210 vf.3 vf.2 vf.1 vf.0 hf.3 hf.2 hf.1 hf.0 bit symbol description 7 to 4 vf.3 to vf.0 indicate the low nibble of the value counted by mode detector for 1 vertical ?eld/frame period. 3 to 0 hf.3 to hf.0 indicate the low nibble of the value counted by mode detector for 4 horizontal scanning periods. bit symbol description
1997 dec 12 53 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.1.5 h orizontal free running f requency /p eriod byte r egister (hfp) table 51 horizontal free running frequency/period register byte register (sfr address f6h) table 52 description of hfp bits 19.1.6 h orizontal free running f requency /p eriod and p ulse w idth r egister (hfpopw) table 53 horizontal free running frequency/period and pulse width register (sfr address f7h) table 54 description of hfpopw bits 19.1.7 v ertical free running f requency /p eriod byte r egister (vfp) table 55 vertical free running frequency/period byte register (sfr address f9h) table 56 description of vfp bits 76543210 hfp9 hfp8 hfp7 hfp6 hfp5 hfp4 hfp3 hfp2 bit symbol description 7 to 0 hfp9 to hfp2 indicate the upper byte of the 10 bits for programming the free running hsync output pulse. 76543210 vsel hfp1 hfp0 hopw4 hopw3 hopw2 hopw1 hopw0 bit symbol description 7 vsel indicates whether the internal vertical sync is coming from the external vsync input pin (vsync in / oe) or separated from the composite signal. if vsel = 0, vertical sync coming from the external vsync input pin. if vsel = 1, vertical sync separated from the composite signal. 6 to 5 hfp1 to hfp0 indicate the lower two of the 10 bits for programming the free running horizontal output pulse. 4 to 0 hopw4 to hopw0 indicate the horizontal output pulse width. 76543210 vfp9 vfp8 vfp7 vfp6 vfp5 vfp4 vfp3 vfp2 bit symbol description 7 to 0 vfp9 to vfp2 indicate the upper byte of the 10 bits for programming the free running vertical output pulse.
1997 dec 12 54 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.1.8 v ertical free running f requency /p eriod and p ulse w idth r egister (vfpopw) table 57 vertical free running frequency/period and pulse width register (sfr address fah) table 58 description of vfpopw bits 19.1.9 p ulse generation c ontrol r egister (pulcnt) table 59 pulse generation control register (sfr address fbh) table 60 description of pulcnt bits 76543210 -- vfp1 vfp0 vopw3 vopw2 vopw1 vopw0 bit symbol description 7to6 - reserved. 5 vfp1 indicate the lower two bits of the 10 bits for programming the free running vertical output pulse. 4 vfp0 3 to 0 vopw3 to vopw0 indicate the vertical output pulse width. 76543210 clmpen pattyp vpg pvsi hpg1 hpg0 fbpo phsi bit symbol description 7 clmpen clamping pulse output (clamp) enable . if clmpen = 1, pin pwm8/clamp/p3.0 is switched to the clamp output. if clmpen = 0, the clamp function is disabled. the clamp function always overrides other alternative functions such as pwm8 and p3.0. 6 pattyp basic display patterns selection . if pattyp = 0, the white display pattern is selected. if pattyp = 1, the cross hatch display pattern is selected. 5 vpg vertical pulse output modes selection . if vpg = 0, a free running vertical sync pulse signal is selected. if vpg = 1, a vertical substitution pulse signal is selected. 4 pvsi vertical output pulse polarity selection . if pvsi = 0, the positive polarity is selected. if pvsi = 1, the negative polarity is selected. 3 to 2 hpg1 to hpg0 horizontal pulse output modes selection ; see table 61. 1 fbpo the clamp pulse at the back porch or at the front porch selection . this bit is only valid when clmpen is set high. if fbpo = 1, the horizontal back porch clamp pulse is selected. if fbpo = 0, the horizontal front porch clamp pulse is selected. 0 phsi polarity of the horizontal and clamping output pulse indication. if phsi = 0, the positive polarity is selected. if phsi = 1, the negative polarity is selected.
1997 dec 12 55 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 table 61 horizontal pulse output modes hpg1 hpg0 modes 0 0 free running horizontal sync pulse signal 0 1 horizontal substitution pulse signal 1 0 reserved 1 1 the incoming horizontal sync is followed and delivered out but the horizontal substitution pulse is disabled, while the incoming hsync is missing
1997 dec 12 56 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2 system description d book, full pagewidth mgg036 5 10 12 4 10 12 hper hper hper 12 hsync_p hpol hpres vper vpol vpres vpol hpol vper fbpo 12 hper hper or hpol change hpol hpres 12 vper vper or vpol change vpol vpres 12 12 hfp9 to hfp0 vfp9 to vfp0 10 10 controls mux mux mux pvsi phsi v-pulse generator v-mode detection capture registers h-pulse generator h-mode detection vpg hpg1 to hpg0 hfp9 to hfp0 vfp9 to vfp0 hopw4 to hopw0 vopw3 to vopw0 vsync out vsync in f clk fosh fosv hsync out clamp mux hsel hsync in csync in sync separation vsync polarity correction mode detect and pulse generation control hsync polarity correction h v div 2 xsel div 76 microcontroller core microcontroller core chreq (change interrupt request) fig.27 block diagram of the hardware mode detection and pulse generation.
1997 dec 12 57 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2.1 c lock prescaler to reach the required 12 bit accuracy and the reasonable crystal clock frequency, the line time of 4 consecutive lines is measured (see section 19.2.5). doing so the maximum crystal clock frequency is: from the calculation above it is clear that there will be no overflow if f clk is 10 or 12 mhz. however, for a 16 or 24 mhz crystal f clk has to be divided by a factor of 2 to get a correct clock frequency fosh for the horizontal part of the mode detection. if f clk used is 10, 12 or 16 mhz then fosh will be respectively 10, 12 or 8 mhz. the same holds for the vertical part of the mode detection. here the minimum vertical sync frequency f v(min) =40hz, so the maximum clock frequency to avoid overflow in a 12-bit counter, equals: to get a maximum accuracy without overflow the clock of the horizontal section fosh, should be prescaled down to this value of fosv. thus the scale factor should be at least: take n = 76 as a suitable scale factor as shown in fig.23. table 62 clock frequencies 19.2.2 h orizontal polarity correction in order to simplify the processing in the following stages, the hsync polarity correction circuit is able to convert the input sync signals to positive polarity signals in all situations. however, be aware that this correction is achieved by the aid of hpol and hper signals. hpol and hper are only settled down in several horizontal scanning lines (61 lines, if f hsync goes up) or a few milliseconds (worst case 1.2 ms, if f hsync becomes inactive) after power-on or timing mode change. f clk (mhz) fosh (mhz) fosv (mhz) 10 10 131.6 12 12 157.9 16 8 105.3 f clk 2 12 f h(min) 4 ----------------------------- - 15.36 mhz = ? ? ?? fosv 2 12 f v(min) 163.84 khz = ? ?? n fosh max () 163.84 khz ------------------------------ - 12 10 3 khz 163.84 khz ---------------------------------- - 73.2 == ? ?? 3 19.2.3 v ertical polarity correction the purpose of the vertical polarity correction is similar to the horizontal polarity correction. however, it takes a longer time to get the correct result after power-on or a timing mode change because at least 5 frames are needed to stabilize vper from the input sync signals. 19.2.4 v ertical sync separation this function will separate the vertical sync out of the composite sync. to do so the change in polarity during vsync interval can be utilized to extract vsync as shown in fig.28. the differentiated sync pulse derived from hsync_p is used to reset an 8-bit upcounter. at 1 4 of the line time the level of the incoming sync at that moment is clocked into the last d flip-flop. be aware that 1 4 of the line period equals 1 16 of parameter hper because hper is calculated based on 4 consecutive lines. due to the fact that the differentiator reacts upon every low-to-high transition even an interlaced composite sync will be separated correctly. note further that the sync separation is taken from signal hsync_p which is processed by the horizontal polarity correction circuit but not necessary with the fixed polarity. as a result the polarity of the separated vertical sync vsep will vary with the incoming composite signal, and in case no composite sync is present the level will be low. according to this algorithm, vsep will be always 1 4 hsync period shift to the original vsync window. the 8-bit counter in fig.28 is stopped at its maximum of ffh, otherwise it will start again from zero which results in a wrong enable pulse for the d flip-flop. all kinds of composite sync input shown in chapter 27 can be dealt with by this function. there are 6 types of composite sync waveforms which can be accepted by the sync processor (see fig.39).
1997 dec 12 58 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2.5 h orizontal mode detection this function block determines the following 4 parameters: hper, hpol, hpres and hcha. the functional block diagram is shown in fig.29. the 12-bit counter for the determination of the horizontal period has a synchronous reset and will be reset by the prescaled and differentiated horizontal pulse hsync_p, coming from the horizontal prescaler, or in case the counter reaches the value ff0h as defined by the comparator. the latter situation will occur if no sync pulses are coming in or if the frequency of the incoming sync pulses is too low. the 12-bit register, that will store the 4 line time period, is only enabled if the signal hena is high. 19.2.5.1 parameter hper based on this configuration, the resulting accuracy for hper will be: accuracy in h table 63 accuracies xtal (f clk ) (mhz) fosh (mhz) accuracy in h at 30khz (%) accuracy in v at 50hz (%) 10 10 0.075 0.038 12 12 0.063 0.032 16 8 0.094 0.048 fig.28 vertical sync separator. handbook, full pagewidth mgg037 8-bit counter e r q7 to q0 differentiator d-ff d e q comparator for sync separation div 16 vsep hsync_p fosh hper 100% (horizontal counter value) ------------------------------------------------------------------- = 100% f h 4fosh -------------------------- =
1997 dec 12 59 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 a 12-bit counter is used to measure the frequency of hsync. every 4 hsync periods are measured and compared with the previous locked hsync frequency; the counter is reset every 4 hsync periods. the base clock to the counter is for a 12 mhz system clock. if the new hsync frequency is larger than the previous hsync frequency, there is a 4-bit counter to avoid the noise or the temporary frequency shift. when the 4-bit counter counts up to 15 for the comparison hfreq (new) > hfreq (previous) , then the mode change interrupt is issued. the time from mode change to interrupt issued is approximately 4 hperiod (new) 15 or (4 hperiod (new) 14)+n hperiod (previous) ), where n = 1, 2 or 3. if the new hsync frequency is not in the static state and is smaller than the previous hsync frequency, the time from mode change to interrupt issued is approximately (4 hperiod (new) 3) - (n hperiod (previous) ), where n = 1, 2, 3 or 4. the static state is considered as the state where the 12-bit counter, for measuring the hsync frequency, reaches 4080. for a 12 mhz system clock, the static state is equal to . if the input hsync frequency is less than 11.8 khz, it will be regarded as static state. a 2-bit counter is used to avoid the noise or the temporary shift. when the 2-bit counter counts up to 3 for the comparison static state < hfreq (new) < hfreq (previous) , then the mode change interrupt is issued. 1 12 mhz ------------------ - 83 ns = 1 83 ns 4080 4 ------------ - -------------------------------- - 1 84660 ns ----------------------- 11.8 khz == when the new input hsync is changed to a static state, the hsync frequency counter reaches 4080. in order to have a faster response of the mode change interrupt, the 2-bit counter is not used and the mode change interrupt is issued immediately. the time from mode change to interrupt issued is approximately ((4080 + 5) 83 ns) - (n hperiod (previous) ), where n = 1, 2, 3 or 4. 19.2.5.2 parameter hpres the presence indicator hpres, as stored in the sr flip-flop, contains some hysteresis, as required due to the two threshold settings in the comparator. the sr flip-flop will be set, indicating that no active sync (or sync with a too low frequency) is coming in if the counter reaches a value of ff0h (4080 decimal). the corresponding horizontal sync frequency is: the sr flip-flop will be reset, indicating that an active sync is present, if the counter reaches a value lower than fc0h (4032 decimal). the corresponding horizontal sync frequency is: the hysteresis result, , is shown in table 64. f h hfreq1 4 fosh counter value () ------------------------------------------- - 4 fosh 4080 --------------------------- == = f h hfreq2 4 fosh counter value () ------------------------------------------- - 4 fosh 4032 --------------------------- == = hysteresis hfreq1 hfreq2 C () hfreq1 = table 64 hysteresis in the hpres detection xtal (f clk ) (mhz) fosh (mhz) hfreq1 (mhz) hfreq2 (mhz) hysteresis (%) 10 10 9.804 9.921 1.2 12 12 11.765 11.905 1.2 16 8 7.843 7.937 1.2
1997 dec 12 60 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2.5.3 parameter hpol the mode change interrupt will be issued after 36 to 40 periods of the hsync when the polarity is changed from negative to positive. the polarity indicator hpol will be changed from a logic 1 to a logic 0. the mode change interrupt will be issued after the 60 periods of the hsync when the polarity is changed from positive to negative. the hpol will be changed from a logic 0 to a logic 1. a logic 0 represents a positive polarity and a logic 1 represents a negative polarity. 19.2.5.4 parameter hcha if hcha is set to high indicating that the period time has changed for a long period, the hper and hpres will be updated. if the measured period time has become stable then the two counters will start to count down and the hena signal is set to low again, thereby disabling the register hper and the sr flip-flop for hpres parameter. fig.29 horizontal mode detection. handbook, full pagewidth mgg038 d-ff sr-ff d e q q hper and hpol decision circuit div 16 hpol fosh fosh hena hcnt hcha fosh hsync hsync_p hres s r hpres hper q hhgh hlow 12-bit counter rq 11 to q0 fosh 12-bit register hper change detector mode change stabilization and comparison circuit d11 to d0 e q11 to q0
1997 dec 12 61 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2.6 v ertical mode detection to detect the vertical mode parameters vper, vpol and vpres, a circuit can be used which is almost similar to that for the horizontal mode detection. the only difference is that now the period time of one frame (instead of 4 lines) is measured. the presence indication for the vertical sync also contains a hysteresis of about 1.2%. the formula to calculate the hysteresis is also similar to the condition of hsync processing. a 12-bit counter is used to count the clock number during one frame. again ff0h (4080 decimal) and fc0h (4032 decimal) are taken as the threshold for vfreq1 and vfreq2 respectively, but the clock fosv = fosh/76. vfreq1, vfreq2 and hysteresis are calculated as follows: f v vfreq1 fosv counter value () ------------------------------------------- - fosh 76 4080 ------------------------- - == = f v vfreq2 fosv counter value () ------------------------------------------- - fosh 76 4032 ------------------------- - == = the hysteresis result, , is shown in table 64. if the new vsync frequency is larger than the previous vsync frequency, the time from mode change to interrupt issued is approximately from ((vperiod (new) 2) + vperiod (previous) ) to (vperiod (new) 3). if the new vsync frequency is not in the static state and is smaller than the previous vsync frequency, the time from mode change to interrupt issued is approximately from vperiod (new) to vperiod (new) 2. if the new vsync frequency is in the static state, the time from mode change to interrupt issued is approximately from (4080 6.3 us) - vperiod (previous) to 4080 6.3 m s. hysteresis vfreq1 hfreq2 C () hfreq1 = table 65 hysteresis in the vpres detection (f clk ) (mhz) fosh (mhz) vfreq1 (mhz) vfreq2 (mhz) hysteresis (%) 10 10 32.25 32.63 1.2 12 12 38.70 39.16 1.2 16 8 25.80 26.11 1.2 the polarity can be measured by looking to the level of the input sync at 1 4 of the frame time. the mode change in vertical the frame period will be detected if there is a change for a longer time than 3 frame periods. the accuracy of vper can calculated by the following formula: the hysteresis results and the accuracy of vper are shown in table 63. 19.2.7 h orizontal pulse generator through the control flags, hpg1 and hpg0, the horizontal pulse generator is able to generate the hsync out signal with the following formats: 1. the same pulse as the input horizontal sync, or a substitution pulse (with a fixed length) in case of a missing sync pulse. accuracy in v 100% (vertical counter value) ------------------------------------------------------------ 100% f v fosv () -------------------------- 100% 76 f v fosh () --------------------------------------- == = 2. a pulse starting at the beginning of the input horizontal sync but now with a fixed length, or a substitution pulse (with fixed length). 3. a free running sync pulse. 4. the same pulse as the input horizontal sync. the substitution pulse is inhibited even if hsync is missing. to be able to generate a substitution pulse the down counter, depicted in fig.23, is loaded at each incoming sync with a period time just a bit longer than the measured hper. if now normal syncs are present then the counter will be loaded just before it reaches 000h. therefore the counter will not generate a pulse (in fig.23, hpst remains low). however, if a sync pulse is missing the counter will reach 000h and generates a substitution pulse, hpst. at the same time it will load itself again for the next run. to generate free running pulses the only thing to do is to load the down counter with the parameter hfp and to stop the load pulses coming from the input sync, hsync_p. so, the signal hpst is either a free running pulse or a pulse in case an input sync is missing.
1997 dec 12 62 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 the 5-bit down counter is used to generate a pulse with pulse width t w(h) . as shown in fig.23, the sr flip-flop will be set by either hpst (free running/missing sync pulse) or by the leading or trailing edge of the incoming sync pulse, hsync_p. in the same way the sr flip-flop will be reset by either the end of the incoming sync pulse or by the pulse width counter. if necessary (hpg1, hpg0: 1, 1), the substitution pulse can be suppressed and only the incoming hsync pulse will be delivered out. the frequency of the free running pulse is: the pulse width of the free running mode is: t w(h) =t fosh (hopw<4:0>) f h(free) fosh hfp ---------------- = fig.30 horizontal pulse generator. handbook, full pagewidth mgg039 q hsync_p hfp hper hpg1 to hpg0 s sr-ff r q hopw fosh data load decision pulse rise/fall generator pulse width generator fosh phsi down counter comparator d9..0 hpst hsync out l q9..0 '0' 19.2.8 v ertical pulse generator the clock used in this vertical pulse generator must be switchable between fosv (needed to generate missing sync pulses) and hpst (free running syncs from the horizontal pulse generator) needed in the free running mode. in the latter situation one vertical sync pulse (i.e. one frame) will be generated by including an integer number of the horizontal scanning lines (i.e. hpst). in this case, the pulse width is also counted by hpst. the rest is more or less equal to the horizontal pulse generator. the frequency of the free running pulse is: the pulse width of the free running mode is: t w(v) =t h(free) [(vopw<3:0>) + 2] 2 f v(free) f h(free) 2vfp ------------------ = 19.2.9 c apture registers this function captures the 6 parameters, hper, hpol, hpres, vper, vpol and vpres such that the current value of these parameters is available for the microcontroller core (software) at all times. the mode change interrupt will be activated if: the horizontal period changes the vertical period changes the horizontal polarity changes the vertical polarity changes. 19.2.10 c ontrol all necessary control signals for the complete hardware mode detection are mentioned in section 19.1.
1997 dec 12 63 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.2.11 t he d isplay p attern g eneration for certain events such as disconnection with the host or the life test of monitor sets, it is convenient to have certain display patterns shown on the monitor as the indication of the operation of the monitor. the p83c880 provides two simple patterns, the white pattern and the cross hatch pattern for this purpose in the free running mode. in the free running mode, the intervals of hsync and vsync are determined by the 10-bit registers, hfp and vfp. based on the hfp and vfp, the internal down counter will determine the starting or ending of the hsync and vsync. the starting position, ending position and the duration of the adjacent hatch lines are all related to the programmed value of hfp and vfp. as a matter of fact, the starting and ending position of the white pattern are decided by the fixed number of fosh clock and fosv clock (see fig.31). therefore, the position or dimension of the white pattern is much related to hfp and vfp. the duration of every two hatch lines (accordingly, the number of hatch lines in the horizontal or vertical direction) will depend on two fixed numbers (32, 32) which divide hfp and vfp. for both white and cross hatch patterns, the displayed pattern might look different in the different timing modes and the symmetric display is not guaranteed. however, they should be sufficient to be used as the indicator to report the status of the monitor. figure 31 demonstrates the display of the two patterns. two flags: patena (sfr pwme2) and pattyp (sfr pulcnt), are used to control the pattern display; for detailed usage of those control bits refer to section 7.3.6 and section 19.1.9. fig.31 two self test display patterns. handbook, full pagewidth mgg040 32 hpst 32 hpst 16 hpst 32 fosh 16 fosh 32 fosh 32 fosh 2. the cross hatch 1. the white pattern 16 fosh 19.2.12 clamp output to facilitate the video processing in the following stage, the clamping pulse can be delivered on pin pwm8/clamp/p3.0 by setting flag clmpen (pulcnt.7) to high. the clamping pulse always accompanies the hsync out pulse. therefore, even in the free running mode the clamping pulse is still present as long as the clmpen bit is set. flag fbpo (pulcnt.1) can be used to choose the front porch clamp pulse (fbpo = 0) or the back porch clamp pulse (fbpo = 1). the pulse width of the clamping output signal is fixed to 8 fosh clocks. the bit phsi (pulcnt.0) is used to set the output polarity of hsync out and the clamping pulse. if phsi is low then the output polarity will be positive, otherwise the output polarity is negative.
1997 dec 12 64 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 19.3 system operation after a successful power-on reset, the p83c880 will automatically start the mode detection and sync separation by default. the output pulses of hsync and vsync are delivered in the free running format by the default setting. since it takes at least 5 frames to finalize the calculation of the hsync period, hper, vsync period and vper, it is better to wait until the stable state is reached to get the complete information after power-on reset. accordingly, hpol, vpol, hpres, vpres and sync separation will be decided upon after hper and vper are settled. to prevent interfering the cpu too often, the interrupt request flag ie0 (sfr tcon) is only set if the mode (including frequency or polarity) is changed. ie0 will be cleared either by the cpu when the service routine is called (it0 = 1) or by the service routine itself (it0 = 0). if it is required to reduce power dissipation or if it is preferred to stabilize the entire system after power-on reset before mode detection is proceeded, the bit march (sfr mdcst) can be cleared to logic 0. mode detection can be activated at the desired moment later on by setting march to a logic 1. in fact, the detection of the device power management signalling (dpms) modes like normal, standby, suspend, power off, etc. and sync separation are mixed together with the display mode detection. the mode detection function provides the hardware vehicle to facilitate the mode detection and related activities. nevertheless, to use this facility to a maximum, the proper interaction between software and hardware is still essential. when vsync is absent and hsync is present, the polarity of hsync is always fixed. a software flow chart example is illustrated in fig.32. 19.3.1 d isplay p ower m anagement s ignalling (dpms) specification according to the dpms specification: hfreq <10 khz and vfreq <10 hz indicates that hsync and vsync are inactive. however, in the real application, there are no modes running with 10 khz hfreq 15 khz and 10 hz vfreq 40 hz. therefore, hfreq = 15 khz and vfreq = 40 hz are chosen as the threshold to indicate an active or inactive signal for hsync and vsync respectively.
1997 dec 12 65 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.32 software procedure in system operation: mode detection flow chart. handbook, full pagewidth mgg041 if csync in? (check hsel) set hsel = 0 set vsel = 0 is vpres = 1? is hpres = 1? no yes set hsel = 1 set vsel = 1 change vsel = 1 change vsel = 0 no yes no yes is vsel = 1? is vpres = 1? yes no no yes interrupt occurs ie0 is set return
1997 dec 12 66 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 20 power management the p83c880 supports power management. the hardware mode detection complies to the device power management signalling (dpms) according to the specification of vesa. the microcontroller is able to distinguish between normal, standby, suspend and power off mode by detecting the frequency of hsync and vsync. hsync is an active signal if its frequency is above 15 khz; otherwise, it is inactive. for vsync 40 hz is the threshold to judge if it is active or inactive. see also section 19.3.1. the exact values for the threshold depend on the chosen crystal oscillator frequency: 10, 12 or 16 mhz. the information about the status of hsync and vsync can be represented by the bits, hpres and vpres in sfr mdcst (address f8h). the combination of hpres and vpres in relation to the operating mode is shown in table 66. in the case of ddc2ab protocol, apart from hardware mode detection, the protocol of access.bus also supports device power management signalling (dpms) commands. in some operating modes the microcontroller might enter a kind of power saving mode, i.e. idle or power-down mode. in this situation the extremely low retention voltage of 1.8 v for internal memory can support the microcontroller to save its state before switching to idle or power-down mode. one set of i/o ports with the capability to drive leds can help to highlight the current operating mode of monitors. it is also possible to control the power consumption sources like heater, main supply etc., through an i/o port in a related operating mode. table 66 display power management modes operating modes hsync hpres vsync vpres normal active 1 active 1 standby inactive 0 active 1 suspend active 1 inactive 0 power off inactive 0 inactive 0 21 control modes the microcontroller can operate in different control modes (e.g. for emulation or otp programming) by means of a 10-bit serial code that is shifted into the reset input. the signal at the xtal1 pin serves as the shift clock. the code is built up as follows: 0 xxxxx 0101; whereby the first 0 is the start bit, followed by a 5-bit code and completed by 0101. the 5-bit code determines the mode. normal mode is reached when no code is shifted in, but the reset pin remains high for at least 10 cycles of the xtal1 input plus 20 m s. when an otp programming/verification, emulation or a test mode should be entered, the timing must be as shown in fig.34. the reset signal is sampled on the rising edge of xtal1. set-up and hold times for the reset signal with respect to the xtal1 rising edge are 10 ns each. the procedure to enter a specific control mode is as follows: 1. reset the microcontroller (cpu) by keeping the reset signal high for at least 10 xtal1 clock cycles to escape any other control mode, plus at least 20 m s (minimum of 24 internal clock cycles) to reset the internal logic. 2. shift in the specific code for the required control mode (e.g. 0 11000 0101 for emulation mode) via the reset pin and the xtal1 clock (msb first). 3. after the 10th bit the reset signal should go low within 9 cycles of xtal1, otherwise the microcontroller will enter normal mode. for the otp programming/verification control modes see chapter 22.
1997 dec 12 67 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 22 one time programmable (otp) version the otp version P87C380 contains: 32 kbytes rom 512 bytes ram. next to the 32 kbytes rom, another extra 384 bytes are available. these bytes can be used for identification purposes or to indicate the version number, etc. these bytes are addressed via address lines a0 to a4. access to the otp for program execution is done in normal mode. for writing and reading (verification) of the program memory and of the extra 384 bytes, different control modes are used as shown in table 67. the signals and waveforms are given in table 69 and fig.33. pin connections to be used during programming and verification are given in table 68. table 67 code for programming/veri?cation of the otp version p87c180a memory code rom: 32 kbytes (program memory) 010000 0101 extra 384 bytes (memory) 010001 0101 rom: 32 kbytes (veri?cation) 011111 0101 table 68 pin assignments during programming/veri?cation mode pin connect to 1v ss 2v ss 3 a13 4 a12 5a11 6 a10 7a9 8a8 9 xtal1 (note 1) 10 xtal2 (note 1) 11 v dd 12 v ss 13 we 14 di5/do5 15 di6/do6 16 oe 17 di4/do4 18 a7 19 a6 20 a5 21 a4 22 a3 note 1. for driving the oscillator pins see fig.10c. 23 a2 24 a1 25 a0 26 reset 27 v ss 28 v ss 29 v ss 30 v ss 31 v ss 32 v dd 33 v ss 34 a14 35 v pp 36 di3/do3 37 di2/do2 38 di1/do1 39 di0/do0 40 di7/do7 41 v ss 42 v ss pin connect to
1997 dec 12 68 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 table 69 timing table for programming; see fig.33 symbol parameter min. typ. max. unit t su(aw) address set-up time write 2 --m s t h(aw) address hold time write 10 --m s t su(ar) address set-up time read 10 -- ns t h(ar) address hold time read 200 -- ns t su(d) data set-up time 2 --m s t h(d) data hold time 20 --m s t su(prog) programming voltage set-up time 10 --m s t h(prog) programming voltage hold time 10 --m s t w(prog) programming pulse width 90 --m s t w(r) read pulse width 300 -- ns t acc(oe) output enable access verify 92 122 183 ns t dz(oe) data ?oat after oe 10 -- ns fig.33 programming waveforms. handbook, full pagewidth mgg051 data out valid data in valid address valid high z v ih v il v pp v pp v il v ih v il v ih v il v ih v il v ih v il we address a0 to a13 data out do0 to do7 data in di0 to di7 oe t su(aw) 10 m s 10 m s t h(aw) t su(ar) t h(ar) t su(d) t h(d) t su(prog) t h(prog) t dz(oe) t acc(oe) t w(r)
1997 dec 12 69 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 23 limiting values in accordance with the absolute maximum rating system (iec 134). 24 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage 4.4 5.5 v v i input voltage (all inputs) - 0.5 v dd + 0.5 v i source(max) total maximum source current for all port lines 0.50 0.67 ma i sink(max) total maximum sink current for all port lines 155 165 ma p tot total power dissipation 88.4 170 mw t stg storage temperature - 60 +150 c t amb operating ambient temperature (for all devices) - 25 +85 c fig.34 timing for otp programming/verification. h andbook, full pagewidth reset 93 xtal1 code 5 xtal1 4 xtal1 4 xtal1 8 xtal1 4 xtal1 x x x x x 00101 xtal1 mbk517
1997 dec 12 70 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 25 dc characteristics v dd = 4.5 to 5.5 v; v ss =0v; t amb = - 25 to +85 c; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 4.4 5 5.5 v i dd operating supply current f clk = 12 mhz 20.1 29.4 30.9 ma f clk = 16 mhz 25.2 36.1 38.4 ma v por power-on-reset voltage level 3.6 3.9 4.2 v p rogramming supply v dd(p) supply voltage programming mode 4.4 5.0 5.5 v v pp programming voltage 12.0 12.75 13.0 v i dd(p) supply current programming mode 10.6 19.1 24.0 ma i pp programming current 77.8 80.1 81.3 ma reset r i(reset) input resistance reset v dd = 4.5 v to 5.5 v 20 60 180 k w i li input leakage current v ss 1997 dec 12 71 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 i oh high-level pull-up output source current strong pull-up during 2 clock cycles v o =v dd - 0.4 v 1.6 -- ma weak pull-up v o =v dd - 0.4 v 25 -- m a port 1: scl/p1.0, sda/p1.1, scl1/p1.2 and sda1/p1.3 v il low-level input voltage v ss - 0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.5 v i li input leakage current v i = 0.4v dd ; v dd =5v - 10 -- 100 m a i it input transition current v i = 0.5v dd ; v dd =5v --- 1000 m a i ol low-level output sink current v o = 0.4 v; v dd = 5v 3.0 -- ma i oh high-level pull-up output source current strong pull-up during 2 clock cycles v o =v dd - 0.4 v 1.6 -- ma weak pull-up v o =v dd - 0.4 v 25 -- m a port 1 and 3: vsync out /p1.4, hsync out /p1.5, pwm10/p1.7 and adc0/p3.2 to adc1/p3.3 v il low-level input voltage v ss - 0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.5 v i li input leakage current v i = 0.4v dd ; v dd =5v - 10 -- 100 m a i it input transition current v i = 0.5v dd ; v dd =5v --- 1000 m a i ol low-level output sink current v o 0.4 v 1.6 -- ma i oh high-level pull-up output source current strong pull-up during 2 clock cycles v o =v dd - 0.4 v 1.6 -- ma weak pull-up v o =v dd - 0.4 v 25 -- m a port 2 and 3: p2.0/pwm0 to p2.7/pwm7 and port p3.0/pwm8/clamp to p3.1/pwm9/patout v il low-level input voltage v ss - 0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd - v dd + 0.5 v i li input leakage current v i = 0.4v dd ; v dd =5v - 10 -- 100 m a i it input transition current v i = 0.5v dd ; v dd =5v --- 1000 m a i ol low-level output sink current v o 0.4 v 1.6 -- ma i oh high-level pull-up output source current strong pull-up during 2 clock cycles v o =v dd - 0.4 v 1.6 -- ma weak pull-up v o =v dd - 0.4 v 25 -- m a symbol parameter conditions min. typ. max. unit
1997 dec 12 72 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 note 1. this maximum applies at all times, including during power switching, and must be accounted for in power supply design. during a power-on process, the +12 v source used for external pull-up resistors should not precede the v dd of the p83c880, p83c180, p83c280 and p83c380 up their respective voltage ramps by more than this margin, nor, during a power-down process, should v dd precede +12 v down their respective voltage ramps by more than this margin . 26 digital-to-analog converter characteristics v dd =5v; v dda =5v; t amb =27 c. note 1. the negative value denotes that the current is sourcing out from the chip into the load device through the output pin. int1/v pp v il low-level input voltage v ss - 0.5 - 0.2v dd - 0.1 v v ih high-level input voltage i ih = 2 ma 0.2v dd + 0.9 - 12.6 v v ih - v dd input voltage with respect to v dd -- 8v symbol parameter test condition min. typ. max. unit v dd supply voltage 4.4 - 5.5 v res dac dac resolution - 8 - bit i o(dac) operating current for each dac channel output pin connected to v dda via 40 k w -- 2.5 ma i o(dac)(id) dac idle current all 4 dac channels shut-down -- 61 m a v o(dac) dac output level voltage output pin open 0 - v dda v at ffh code input; i oh = - 1ma (note 1) v dda - 0.2 -- v at 00h code input; i ol = 1ma -- 0.2 v dl e differential non-linearity output level 0.2 to 4.8 v - 1 - +1 lsb t st settling time -- 20 ms d v o(t) output voltage variation due to temperature drift -- 1.5 mv/ c d v o output voltage ripple t test >20ms -- 2mv symbol parameter conditions min. typ. max. unit
1997 dec 12 73 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 27 ac characteristics v dd = 4.5 v to 5.5 v; v ss =0v; t amb = - 25 to + 85 c; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit f clk crystal oscillator frequency v dd =5v 101216mhz f pxe pxe resonator frequency v dd = 5 v 10 12 16 mhz c xtal1 external capacitance at xtal1 with crystal resonator - 20 27 pf with pxe resonator - 20 27 pf c xtal2 external capacitance at xtal2 with crystal resonator - 20 27 pf with pxe resonator - 20 27 pf analog-to-digital converter (software) v in(a) comparator analog input voltages adc0; adc1 v ss - v dd v v ae conversion error range -- 1 2 lsb t conv(adc) conversion time (from any change in adc input i.e. voltage level) -- 7 m s ddc1 mode (1) (transmit-only, unidirectional); see figs 25 and 35 t dov output valid from vclk -- 30 m s t vclkh vclk high time 20 --m s t vclkl vclk low time 20 --m s t t(mode) mode transition time -- 800 ns t sup(input) input filter spike suppression; for sda, scl and vsync -- 200 ns t su(ddc1) ddc1 mode set-up time - 5 -m s horizontal sync input for the mode detection; see fig.36 hfreq hsync input frequency 15 - 150 khz t w(hsync) hsync input pulse width notes 2 and 3 0.25 - 8 m s h dcyc hsync input duty cycle notes 2 and 3 -- 25 % t ir(hsync) hsync input rise time -- 100 ns t if(hsync) hsync input fall time -- 100 ns vertical sync input for the mode detection; see fig.37 vfreq vsync input frequency 40 - 200 hz t w(vsync) vsync input pulse width note 4 1 - 24 note 5 v dcyc vsync input duty cycle note 4 -- 25 % t ir(vsync) vsync input rise time -- 100 ns t if(vsync) vsync input fall time -- 100 ns
1997 dec 12 74 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 notes 1. for the ddc2 mode (bidirectional i 2 c-bus mode), refer to the standard i 2 c-bus specification. 2. the actual sync width has to fulfil both requirements, maximum pulse width t w(hsync) = 8.0 m s and maximum duty cycle h dcyc of 25%, at the same time. 3. the polarity of the horizontal sync pulse is said to be positive if the high period is shorter than the low period. 4. the actual sync width has to fulfil both requirements, maximum pulse width t w(vsync) = 24 horizontal line periods and maximum duty cycle v dcyc of 25%, at the same time. composite sync input for the mode detection; see figs 38 and 39 t eq(csync) equalizing pulse period for csync input - 0.5 - note 5 t weq(csync) equalizing pulse width for csync input - 0.5 - note 6 neq equalizing pulses plus the vsync interval -- 30 note 5 horizontal and vertical pulse generation; see figs 40 and 41 t h(free) horizontal pulse period in free running 10 - 66 m s t wh(free) horizontal pulse width in free running 0.4 - 2.5 m s t or(hsync) hsync output pulse rise time 30 31 32 ns t of(hsync) hsync output pulse fall time 24 26 28 ns t d(in-out)(hsync) hsync output delay to input -- 100 ns t dmax(hsyncm) hsync output maximum delay after missing hsync -- 350 ns t w(hsyncsub) hsync output substitution pulse width -- 2.5 m s t d(hsync-clamp) clamp pulse delay to hsync input 0- 125 ns t w(clamp) clamp pulse width 0.4 - 2.5 m s t v(free) vertical pulse period in free running -- 2048 note 5 t wv(free) vertical pulse width in free running -- 32 note 5 t or(vsync) vsync output pulse rise time 22 24 26 ns t of(vsync) vsync output pulse fall time 24 27 30 ns t d(in-out)(vsync) vsync output delay to input -- 250 ns t dmax(vsyncm) vsync output maximum delay after missing vsync -- 1 note 5 t w(vsyncsub) vsync output substitution pulse width -- 16 note 5 slope control port t tlh(sce) low-to-high transition delay while slope control enabled 0.1v dd to 0.9v dd ; note 7 25 - 100 ns t thl(sce) high-to-low transition delay while slope control enabled 0.9v dd to 0.1v dd ; note 7 25 - 100 ns t plh(scd) low-to-high propagation delay while slope control disabled 0.1v dd to 0.9v dd ; load = 50 pf -- 10 ns t phl(scd) high-to-low propagation delay while slope control disabled 0.9v dd to 0.1v dd ; load = 50 pf -- 10 ns symbol parameter conditions min. typ. max. unit
1997 dec 12 75 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 5. unit is hsync line period: t line(hsync). 6. unit is hsync pulse width: t w(hsync) . 7. this transition delay has to be loaded independent for capacitances up to 50 pf. fig.35 mode transition from ddc1 to ddc2. handbook, full pagewidth mgg052 t t(mode) transmit only mode (ddc1) bidirectional mode (ddc2) scl sda vclk fig.36 horizontal sync input signal. handbook, full pagewidth mgg053 hsync t w(hsync) h dcyc t if(hsync) t ir(hsync) t hsync fig.37 vertical sync input signal. handbook, full pagewidth vsync t if(vsync) t ir(vsync) t vsync mgg054 t w(vsync) v dcyc
1997 dec 12 76 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.38 standard composite sync pulse wave forms. handbook, full pagewidth mgg055 hsync hsync csync csync vsync t w(csync) t weq(csync) t eq(csync) 2nd field 1st field vsync 2nd field 1st field 1 / h freq neq
1997 dec 12 77 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.39 composite sync pulse wave forms. handbook, full pagewidth mgg056 t w(hsync) 1/h freq t w(vsync) t weq(csync) t eq(csync) neq hsync vsync csync-1 csync-2 csync-3 csync-4 csync-5 csync-6
1997 dec 12 78 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.40 horizontal sync output pulse. handbook, full pagewidth mgg057 t w(clamp) t w(clamp) t d(hsync-clamp) t d(hsync-clamp) t w(hsyncsub) t w(hsyncsub) t w(hsyncsub) t dmax(hsyncm) t dmax(hsyncm) t d(in-out)(hsync) t wh(free) t or(hsync) t of(hsync) t h(free) hsync hsync out (free running) hsync out (sync/ substitution) hsync out (sync/substitution with fixed pulse width) clamp (clamp pulse at back porch) clamp (clamp pulse at front porch)
1997 dec 12 79 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 fig.41 vertical sync output pulse. handbook, full pagewidth mgg058 t w(vsyncsub) t dmax(vsyncm) t d(in-out)(vsync) t wv(free) t or(vsync) t of(vsync) t v(free) vsync vsync out (free running) vsync out (sync/ substitution)
1997 dec 12 80 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 28 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1997 dec 12 81 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 29 soldering 29.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 29.2 soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 29.3 repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
1997 dec 12 82 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 30 definitions 31 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 32 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 dec 12 83 philips semiconductors product speci?cation microcontrollers for monitors with ddc interface, auto-sync detection and sync proc. p83cx80; P87C380 notes
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